|
|
AVR32 Model Coreation
Sarčák, Rostislav ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
This barchelor's thesis describe creation of AVR32 processor instruction-accurate model using CodAL language. In this thesis RISC AVR32 architecture, approach to implementation of the model, testing and generating of software toolchain is described. Model development is realized in Codasip framework. Model contains implementation of AVR32 instruction set. The result of this work is AVR32 processor instruction-accurate model.
|
|
|
Design and Implementation of a Profiler for ASIPs
Richtarik, Pavel ; Hynek, Jiří (referee) ; Zachariášová, Marcela (advisor)
The major objective of this work is to analyse possibilities of profiling application specific instruction-set processors, to explore some common profiling techniques and to use the collected information to design and implement a new profiling tool suitable for utilization in the processors development and optimization. This bachelor thesis presents requirements on the new profiler and describes its key parts from the design and the implementation perspective.
|
|
|
RISC-V Processor Model
Barták, Jiří ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
|
|
|
Fast and Partially Translated Simulator for Application-Specific Processors
Richtarik, Pavel ; Krčma, Martin (referee) ; Zachariášová, Marcela (advisor)
The major objective of this work is to analyse possibilities of using simulation within the development of application-specific instruction-set processors, to explore and compare some common simulation techniques and to use the collected information to design a new simulation tool suitable for utilization in the processors development and optimization. This thesis presents the main requirements on the new simulator and describes the design and implementation of its key parts with emphasis on the high performance.
|
|
|
Implementation of General Assembler
Husár, Adam ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
This thesis describes the design of the universal assembler that represents a part of the Lissom project. You will be provided with the description of the assembler architectures and their usual tasks. Special attention is paid to GNU assembler. Designed assembler consists of the fixed and the generated part. The generated part is created automatically from the description of instruction set, that is defined using architecture and instructions set description language ISAC. Using this approach, it is possible to change assembler target architecture automatically. The second part of thesis describes the Parserlib2 library implementation that is a part of the Lissom project and provides the information about the target instruction set for an assembler generator.
|
|
|
NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
|
|
|
Dynamic Reconfiguration of Hardware Accelerators
Brabec, Lukáš ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
Thesis deals with usage of dynamic reconfiguration of FPGA in area of application specific instruction-set processors, considerng time-to-market, possibilities of acceleration and universality. Furthermore, it is designed an extension of application specific processor Codix with reconfigurable unit and it is described its implementation. Finally, the results are evaluated and opportunities for further development are identified.
|
|
|
Acceleration of Applications Using Specialized Instructions
Mikó, Albert ; Krčma, Martin (referee) ; Hruška, Tomáš (advisor)
The design of specialized instructions for application specific processors is a challenging task. This thesis describes the issues of effective specification and use of specialized instructions for optimization of applications. It focuses on improvements of the outputs and usability of the semiatomatic method of selection of specialized instructions to allow the optimization of complicated applications. This method combines manual selection of instructions by marking a section of source code in the application and automatic generation of the instruction description in the modelling language.
|
|
|
Transformation of a Processor Description in CodAL to SystemC Structures
Ondruš, Tomáš ; Hynek, Jiří (referee) ; Přikryl, Zdeněk (advisor)
The goal of this thesis is to create a generator of simulators and hardware representation of application specific processors in a SystemC language. An aim of the first part is to create a wrapper layer compatible with SystemC TLM 2.0 that wraps an existing simulator to avail modeling of transaction oriented systems. The second part is a generator of a hardware representation for the processor that is suitable not only for logical synthesis, but also for the simulation on a cycle accurate level. A final result is a state of the art solution comparable to existing generators.
|
|
|
Genetická analýza zbarvení u huculských koní zařazených do genetického zdroje
Karbusická, Alžběta
In this work, MC1R, ASIP and TBX3 gene were tested on a sample of 118 Hucul horse mares included in Genetic Resources of Animals in the Czech Republic. We want to determine the genetic structure of mares and to analyse phenotypic data compared to the genotype and to identify possible differences between it. Genetic analysis showed a solid state for all alleles (HW for ASIP P = 0.9360, for MC1R P = 0.1661 and for TBX3 P = 0.4444). The frequency of the allele was as follows: E (0.6780), A (0.5254), and (0.4746), d2 (0.4323), d1 (0.3542), e (0.3220) D (0.2135). The most common genotype was AaEed1d2 and AaEEd1d2. There were very few or no genotypes based on recessive homozygotes in the genes of basic coat colours in the population, we didn´t identify any individual with genotype AaEed1d1. We have publicised genotype dependence within the TBX3 gene with primitive markings, confirming the previous work of other. Alele D was always associated with the occurrence of primitive markings, but primitive markings occur even without allele D in coincidence with the d1 allele. The d2d2 genotype is associated with a phenotype without primitive markings, or with phenotype where we can´t say if the horse has primitive markings or not.
|
guest ::
