|
|
High level synthesis in network applications described using P4 language
Panák, Petr ; Šťáva, Martin (referee) ; Fujcik, Lukáš (advisor)
High-level synthesis is a compelling method of designing a digital circuit. High abstraction and faster verification are advantages which aren't pressent in Register Transfer Level designing. That guarantees faster designing with lower development costs. This bachelor thesis deals with a digital design of actions, extern blocks and MI32 interface access. Each component design is described using C/C++ programming language and synthesised with Intel HLS compiler.
|
|
|
P4 cryptographic primitive support
Cíbik, Peter ; Malina, Lukáš (referee) ; Smékal, David (advisor)
This diploma thesis deals with the problem of high-speed communication security which leads to the usage of hardware accelerators, in this case high-speed FPGA NICs. Work with simplification of development of FPGA hardware accelerator applications using the P4 to VHDL compiler. Describes extension of compiler of cryptographic external objects support. Teoretical introduction of the thesis explains basics of P4 language and used technologies. Describes mapping of external objects to P4 pipeline and therefore to FPGA chip. Subsequently deals with cryptographic external object, compatible wrapper implementation and verification of design. Last part describes implementation and compiler extension, cryptographic external object support and summarizes reached goals.
|
|
|
P4 Language-Based Description of Accelerated Device against DoS Attacks
Kuka, Mário ; Kekely, Lukáš (referee) ; Kučera, Jan (advisor)
This thesis describes the development of a networking device used to defend against (D)DoS attacks using P4 language. The main purpose was to design flexible device using P4 lan-guage based on already existing device, this would allow us to quickly react and respond to new more complex DDoS attacks. The design of the device dealt with the transfer of individual parts of the firmware into the P4 language. Subsequently, the entire device firmware was designed for hardware accelerators with FPGA technology. The firmware had been designed with respect to the limitations of current P4 language compilers. The device has been tested under laboratory conditions for functionality and performance. The device will be deployed in the network infrastructure of CESNET.
|
|
|
The Stateful Packet Processing in P4 Language
Kohout, Pavel ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
With the growing speed and complexity of computer networks, arise requirements for creating powerful devices that are capable of collecting statistics and changing their own functionality according to the demands of network administrators. These requirements can be described using specialized programming languages such as P4. In this bachelor thesis a design, implementation, testing and integration of register and counter stateful memory modules into P4 compiler system for FPGA technology was made. The created system supports the collection of statistics described in P4 language at speeds up to 100 Gbps.
|
|
|
Remote Configuration of P4 Device
Neruda, Jakub ; Kučera, Jan (referee) ; Wrona, Jan (advisor)
Administration of a large network from a central node with a vendor independent API is quite important issue these days. The concept of SDN was truly helpful with realization of the solution, namely in the form of the OpenFlow protocol. Nowadays, a P4 language is gaining momentum, primarily thanks to its ability to describe whole packet processing pipeline and also for the P4 Runtime, solution to the distributed network configuration. CESNET association is one of the research groups starting to support P4 in their network cards beloging to the Combo series. In this work, an API was designed for these cards, aimed at the dynamic flow table configuration. This API was used for implementation of a basic support of the Combo cards in the P4 Runtime.
|
|
|
OVS Acceleration Using FPGA Acceleration Card
Vido, Matej ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
The performance of the virtual switch Open vSwitch (OVS) is insufficient to satisfy the current requirements for link bandwidth of the server connections. There is an effort to accelerate the OVS both in the software and in the hardware by offloading the datapath to the smart network interface cards. In this work the COMBO card for 100G Ethernet developed by CESNET is used to accelerate the OVS. The suggested solution utilizes the firmware for FPGA generated from the definition in the P4 language to classify the packets in the card and DPDK for the data transfers and offloading the classification rules into the card. Forwarding of one flow with the shortest frames from physical to physical interface using one CPU core reaches forwarding rate of 11.2 Mp/s (10 times more than the standard OVS) with classification in the card and 5.9 Mp/s without classification in the card.
|
|
|
System for Monitoring of Network Protocols
Selecký, Roman ; Dražil, Jan (referee) ; Kořenek, Jan (advisor)
It is necessary to monitor networks namely for diagnostics, troubleshooting, detection of anomalies and suspicious header encapsulations. This thesis aims to design and implement a system for monitoring protocol structure on 10 Gb networks, which will be able to capture packets based on the sequence of encapsulated protocols. To achieve requested throughput some tasks like packet parsing and packet filtering were accelerated in FPGA. Flexibility is achieved by using a tool that maps P4 programs, which define packet parsing process, to VHDL language. Based on the information gained from packet parsing, flow records are created and stored via IPFIX protocol. This information is displayed through a graphical user interface in the form of protocol tree, whose nodes are associated with flow records.
|
|
|
Packet Parsing and Header Field Extraction in FPGA
Selecký, Roman ; Košař, Vlastimil (referee) ; Kořenek, Jan (advisor)
Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.
|
|
|
Mapping of Match Tables from P4 Language to FPGA Technology
Kekely, Michal ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This thesis deals with design and implementation of mapping of match action tables from P4 language to FPGA technology. Goal of the thesis was to describe key principles, which need to be understood in order to design such a mapping and function of algorithms needed, apply these principles by implementing them and analyze the speed and memory requirements of such an implementation. Outcome provides configurable hardware unit capable of classifying packets and connection between the unit and match action tables from P4 language. The implementation is based on DCFL algorithm and requires less memory compared to HiCuts and HyperCuts algorithms while being comparably fast at worst-case scenarios.
|
|
|
Marketing Mix of a Company On Semiconductor, a.s.
Majeriková, Ela ; Streda, Peter (referee) ; Novák, Petr (advisor)
This bachelor thesis is dedicated to the industrial marketing in comparison to the marketing on the customer markets. The theoretical part concentrates on the theory of marketing, marketing on B2B markets, the differences between consumer and industrial market and marketing mix on B2B markets. In analytical part, the company ON Semiconductor, a.s is introduced along with the marketing mix of SMART METER applications and macroeconomic analysis. On the bases of the results, the PEST and SWOT analysis are conducted. In the implementation part of the bachelor thesis I have drafted the possible solution of the weak points based on the SWOT analysis.
|
guest ::
