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Automated Creation of Portable Stimuli Scenarios Using Evolutionary Algorithms
Tichý, Andrej ; Bardonek, Petr (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on the automation of scenarios creation for Portable Stimulus standard. The main goal of the work is an automatic generation of tests, which are defined as graphs for the Questa inFact tool from the Mentor company. For the automation I used an evolutionary algorithm with using a grammatical evolution. The generated scenarios are connected to the existing verification environment based on UVM methodology, then the verification of the connected component is started. Based on the achieved functional and structural coverage, the individual's fitness value is calculated and propagated into an evolutionary algorithm. At the end of the work, experiments are performed on the timer component and the contribution of the proposed evolutionary algorithm is evaluated. The proposed evolutionary algorithm is configurable by grammar and user-defined basic transactions, which allows a wide range of uses. The evolutionary algorithm managed to achieve high functional and structural coverage on the verified timer component.
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Hardware Accelerated Functional Verification of Processor
Funiak, Martin ; Kajan, Michal (referee) ; Zachariášová, Marcela (advisor)
Functional verification belongs among the current verification approaches. Functional verification checks the correctness of the implementation of the system, due to its specification. The weakness of the functional verification approach is time consumption caused by slow software simulation of implicitly parallel hardware systems. This paper presents a solution for using a hardware accelerated functional verification of the processor. The introductory chapters form the theoretical basis for the following chapters, that include a choice of solutions, an analysis, a design of a verification environment and implementation details. The conclusion includes tests of the final product, evaluation of the results and the future work perspectives.
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Functional Verification of Robotic System Using UVM
Krajčír, Stanislav ; Čekan, Ondřej (referee) ; Zachariášová, Marcela (advisor)
One of the currently most used approaches for verification of hardware systems is functional verification. This master thesis describes design and implementation of a verification environment using UVM (Universal Verification Methodology) methodology for verifying the correctness of the robot controller in order to eliminate functional errors and faults of its implementation. The theoretical part of the thesis describes the basic information about functional verification, methodologies for creating verification environments, the SystemVerilog language and fault tolerance methodologies. The next part of thesis focuses on the design of the verification environment, its implementation and the creation of tests used to verify the correctness of the robot controller. Results of verification are discussed and evaluated in the conclusion of this work.
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Automation of Verification Using Artificial Neural Networks
Fajčík, Martin ; Husár, Adam (referee) ; Zachariášová, Marcela (advisor)
The goal of this thesis is to analyze and to find solutions of optimization problems derived from automation of functional verification of hardware using artificial neural networks. Verification of any integrated circuit (so called Design Under Verification, DUV) using technique called coverage-driven verification and universal verification methodology (UVM) is carried out by sending stimuli inputs into DUV. The verification environment continuously monitors percentual coverage of DUV functionality given by the specification. In current context, coverage stands for measurable property of DUV, like count of verified arithemtic operations or count of executed lines of code. Based on the final coverage, it is possible to determine whether the coverage of DUV is high enough to declare DUV as verified. Otherwise, the input stimuli set needs to change in order to achieve higher coverage. Current trend is to generate this set by technique called constrained-random stimulus generation. We will practice this technique by using pseudorandom program generator (PNG). In this paper, we propose multiple solutions for following two optimization problems. First problem is ongoing modification of PNG constraints in such a way that the DUV can be verified by generated stimuli as quickly as possible. Second one is the problem of seeking the smallest set of stimuli such that this set verifies DUV. The qualities of the proposed solutions are verified on 32-bit application-specific instruction set processors (ASIPs) called Codasip uRISC and Codix Cobalt.
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ASIPs Intelligent Testbench Automation
Badáň, Filip ; Hynek, Jiří (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on the proposal and implementation of intelligent testbench automation for application-specific processors. The main goal of the thesis is to connect UVM verification environment with already designed genetic algorithm and to prepare this verification environment for integration into Codasip Studio development environment. The core of the final solution is modification of UVM components in verification environment and communication between the genetic algorithm and the generator of random test applications.
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Enriching the Process of Verification of RISC-V Processor with Formal Techniques
Horký, Jakub ; Šnobl, Pavel (referee) ; Hruška, Tomáš (advisor)
This thesis provides a brief overview of the RISC-V architecture, design of processors, and how easily a bug can arise during the development. Then this thesis describes the way functional verification tries to discover those bugs and what are its pros and cons. More specifically, the thesis focuses on what the verification environment in UVM look like. Then the thesis describes, how formal verification fits in to the functional verification and shows the tools that are available for formal verification. The final part of this thesis, describes the process of how I wrote the assertions (written in SVA) for a RISC-V processor, using a property checking tool. Using these assertions for verifying a processor in the late stage of development, when functional verification already had the possibility to discover most of the bugs, I still was able to discover few of those bugs.
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UVM Verification of DMA Medusa System
Petruška, Zdenko ; Martínek, Tomáš (referee) ; Kekely, Lukáš (advisor)
This thesis describes design and implementation of verification environment for system DMA Medusa. DMA Medusa is hardware system used for high speed transmissions between network card and RAM. Verification environment is developed in SystemVerilog using UVM. Environment is designed with intention to find functional bugs using top level random stimulus. Testbench requirements have been defined prior to its implementation. Requirements are based on system specification and previous version of testbench. Previous version has been based on different methodology. New testbench implements the functionality of previous one. In addition, some functionality has been exteded. Implemented testbench extends previous memory model by serving memory requests in random order. It also implements functional coverage focused on communication with memory and network card. Goal of functional coverage is to monitor quality of generated stimulus.
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Functional Verification Framework for Multi Buses Following the UVM Standard
Beneš, Tomáš ; Šišmiš, Lukáš (referee) ; Kekely, Lukáš (advisor)
This thesis focus on the design and subsequent implementation of a multi-bus verification environment using the principles of the Universal Verification Methodology (UVM). It also focus on the implementation of the verification of three FPGA components using multi-bus as input and output interfaces. The implementation of the environment and all verifications is written in SystemVerilog language using a library that implement the basic constructs for UVM. The achieved results of the work are functional and easily reusable when creating further verifications using multi-bus. The proposed environments can be used as a structure for creating other verification environments for other buses.
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Automated Creation of Portable Stimuli Scenarios Using Evolutionary Algorithms
Tichý, Andrej ; Bardonek, Petr (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on the automation of scenarios creation for Portable Stimulus standard. The main goal of the work is an automatic generation of tests, which are defined as graphs for the Questa inFact tool from the Mentor company. For the automation I used an evolutionary algorithm with using a grammatical evolution. The generated scenarios are connected to the existing verification environment based on UVM methodology, then the verification of the connected component is started. Based on the achieved functional and structural coverage, the individual's fitness value is calculated and propagated into an evolutionary algorithm. At the end of the work, experiments are performed on the timer component and the contribution of the proposed evolutionary algorithm is evaluated. The proposed evolutionary algorithm is configurable by grammar and user-defined basic transactions, which allows a wide range of uses. The evolutionary algorithm managed to achieve high functional and structural coverage on the verified timer component.
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Portable Stimulus Scenarios Specification for RISC-V Processor Modules
Bardonek, Petr ; Bidlo, Michal (referee) ; Zachariášová, Marcela (advisor)
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.
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