Název: Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain
Autoři: Sýkora, Jaroslav
Typ dokumentu: Příspěvky z konference
Konference/Akce: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Karlovy Vary (CZ), 2013-04-08 / 2013-04-10
Rok: 2013
Jazyk: eng
Abstrakt: We present a technique for modelling and synthesis of fine-grained data-driven circuits in the clock-synchronous hardware, such as the field programmable gate arrays (FPGA), called the Flow-Transfer Level (FTL). The distinguishing property of the FTL technique is that it does not rely on FIFO queues to handle flow synchronization between the components (called operators). The communication channels, called pipes, employ conceptually a two-state handshake protocol. The handshake behaviour of each operator is defined logically using dependency subgraphs that are symmetrical for producers and consumers. The original data-flow netlist of operators is transformed into a global control dependency graph. Cycles in dependency graphs are allowed as long as they do not constitute real data dependencies but only dependencies in promises of handshake completions. A method is given that recursively eliminates these cycles.
Klíčová slova: clock-synchronous hardware; field programmable gate arrays; Flow-Transfer Level
Zdrojový dokument: Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), ISBN 978-1-4673-6133-0

Instituce: Ústav teorie informace a automatizace AV ČR (web)
Informace o dostupnosti dokumentu: Dokument je dostupný na externích webových stránkách.
Externí umístění souboru: http://library.utia.cas.cz/separaty/2013/ZS/sykora-composing data-driven circuits using handshake in the clock-synchronous domain.pdf
Původní záznam: http://hdl.handle.net/11104/0220654

Trvalý odkaz NUŠL: http://www.nusl.cz/ntk/nusl-152761


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