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Original title:
Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain
Authors: Sýkora, Jaroslav
Document type: Papers
Conference/Event: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Karlovy Vary (CZ), 2013-04-08 / 2013-04-10
Year: 2013
Language: eng
Abstract: We present a technique for modelling and synthesis of fine-grained data-driven circuits in the clock-synchronous hardware, such as the field programmable gate arrays (FPGA), called the Flow-Transfer Level (FTL). The distinguishing property of the FTL technique is that it does not rely on FIFO queues to handle flow synchronization between the components (called operators). The communication channels, called pipes, employ conceptually a two-state handshake protocol. The handshake behaviour of each operator is defined logically using dependency subgraphs that are symmetrical for producers and consumers. The original data-flow netlist of operators is transformed into a global control dependency graph. Cycles in dependency graphs are allowed as long as they do not constitute real data dependencies but only dependencies in promises of handshake completions. A method is given that recursively eliminates these cycles.
Keywords: clock-synchronous hardware; field programmable gate arrays; Flow-Transfer Level
Host item entry: Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), ISBN 978-1-4673-6133-0
Institution: Institute of Information Theory and Automation AS ČR (web)
Document availability information: Fulltext is available at external website.
External URL: http://library.utia.cas.cz/separaty/2013/ZS/sykora-composing data-driven circuits using handshake in the clock-synchronous domain.pdf
Original record: http://hdl.handle.net/11104/0220654
Permalink: http://www.nusl.cz/ntk/nusl-152761
The record appears in these collections:
Research > Institutes ASCR > Institute of Information Theory and Automation
Conference materials > Papers
Authors: Sýkora, Jaroslav
Document type: Papers
Conference/Event: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Karlovy Vary (CZ), 2013-04-08 / 2013-04-10
Year: 2013
Language: eng
Abstract: We present a technique for modelling and synthesis of fine-grained data-driven circuits in the clock-synchronous hardware, such as the field programmable gate arrays (FPGA), called the Flow-Transfer Level (FTL). The distinguishing property of the FTL technique is that it does not rely on FIFO queues to handle flow synchronization between the components (called operators). The communication channels, called pipes, employ conceptually a two-state handshake protocol. The handshake behaviour of each operator is defined logically using dependency subgraphs that are symmetrical for producers and consumers. The original data-flow netlist of operators is transformed into a global control dependency graph. Cycles in dependency graphs are allowed as long as they do not constitute real data dependencies but only dependencies in promises of handshake completions. A method is given that recursively eliminates these cycles.
Keywords: clock-synchronous hardware; field programmable gate arrays; Flow-Transfer Level
Host item entry: Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), ISBN 978-1-4673-6133-0
Institution: Institute of Information Theory and Automation AS ČR (web)
Document availability information: Fulltext is available at external website.
External URL: http://library.utia.cas.cz/separaty/2013/ZS/sykora-composing data-driven circuits using handshake in the clock-synchronous domain.pdf
Original record: http://hdl.handle.net/11104/0220654
Permalink: http://www.nusl.cz/ntk/nusl-152761
The record appears in these collections:
Research > Institutes ASCR > Institute of Information Theory and Automation
Conference materials > Papers
Record created 2013-04-17, last modified 2021-11-24