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Automated testbed for SIL/PIL testing of embedded application using FPGA
Prusák, Lukáš ; Burian, František (referee) ; Arm, Jakub (advisor)
The master's thesis deals with designing a testbench for a selected soft-core processor NEORV32 with a RISC-V architecture for simulations of embedded applications in an FPGA environment. The testbench was created in the Vivado environment with the aim of extending it to a testing and validation framework. Basic modules such as GPIO, PWM, UART, and PC were selected and implemented. Several test scenarios have been designed for these modules. The testbench has also been supplemented with additional scripts, to create hierarchically correct project setup and test execution. The work also suggests a few possible ways to improve and expand the testbench.
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Test Driven Development for FPGA Designs
Halász, Dávid ; Strnadel, Josef (referee) ; Šimek, Václav (advisor)
Tato bakalářská práce popisuje, jak může být princip TDD uplatněn u hardware, převážně pro vývoj FPGA. Je popsána důležitá teorie pro pochopení kontextu. Na referenčním návrhu jsou představeny některé dostupné a užitečné verifikační nástroje. Jeden z těchto nástrojů byl vybrán a pomocí TDD byl vytvořen a úspěšně otestován návrh komunikačního modulu SPI.
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STEMLab based data acquisition system
Pavlík, Radim ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
Thesis deals with design of acquisition system, working on developing platform STEMLab (Red Pitaya). Goal is possibility of monitoring analog signals with adjustable sampling frequency and length of acquisition. Software was created for both controlling part (Python application) and for platform itself (embedded C, Python) using the appropriate FPGA-HW design (HDL). Thesis describe how to work with platform ecosystem, control and behaviour of aplications created during the proces of getting acquainted with the platform and options how aplications could be created.
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Design of hardware cipher module
Bayer, Tomáš ; Stančík, Peter (referee) ; Sobotka, Jiří (advisor)
This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.
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Automated testbed for SIL/PIL testing of embedded application using FPGA
Prusák, Lukáš ; Burian, František (referee) ; Arm, Jakub (advisor)
The master's thesis deals with designing a testbench for a selected soft-core processor NEORV32 with a RISC-V architecture for simulations of embedded applications in an FPGA environment. The testbench was created in the Vivado environment with the aim of extending it to a testing and validation framework. Basic modules such as GPIO, PWM, UART, and PC were selected and implemented. Several test scenarios have been designed for these modules. The testbench has also been supplemented with additional scripts, to create hierarchically correct project setup and test execution. The work also suggests a few possible ways to improve and expand the testbench.
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Nový polymorfizmus genu apolipoprotein A2 a jeho asociace s obsahem mastných kyselin u prasat
Sukhov, Oleg
This thesis studies the problematic of the new polymorphism APOA2 gene and that association with fatty acids contain in a group of Czech Large White pigs. APOA2 gene (ID: 100153243) is a candidate gene for porcine meat quality. The aim of thesis was to analyze the influence of selected polymorphisms on fatty acids and intramuscular fat contain. Among fatty acids was observed a contain of: tetradecenoic acid, palmitic acid, palmitoleic acid, stearic acid, oleic acid, linoleic acid, linolenic acid, arachidonic acid, arachidic acid a eicosapentaenoic acid (EPA). Have been used molecular-genetic methods such as primers design in the OLIGO software, PCR, gel electrophoresis a sequencing by Sanger method. The results were processed by form of genotype frequency and followed by associative analysis with a mixed linear model. The values of the relative alleles frequency of polymorphism APOA2 T>A rs80803879 were as follows: A = 0,086, T = 0,914 and relative alleles frequency of APOA2 G>A rs331415849: A = 0,068 a G = 0,948. Polymorphism associations were found for fatty acids: myristoleic acid, acid palmitoleic acid, oleic acid, arachidonic acid, and arachidic acid.
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Test Driven Development for FPGA Designs
Halász, Dávid ; Strnadel, Josef (referee) ; Šimek, Václav (advisor)
Tato bakalářská práce popisuje, jak může být princip TDD uplatněn u hardware, převážně pro vývoj FPGA. Je popsána důležitá teorie pro pochopení kontextu. Na referenčním návrhu jsou představeny některé dostupné a užitečné verifikační nástroje. Jeden z těchto nástrojů byl vybrán a pomocí TDD byl vytvořen a úspěšně otestován návrh komunikačního modulu SPI.
|
|
|
STEMLab based data acquisition system
Pavlík, Radim ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
Thesis deals with design of acquisition system, working on developing platform STEMLab (Red Pitaya). Goal is possibility of monitoring analog signals with adjustable sampling frequency and length of acquisition. Software was created for both controlling part (Python application) and for platform itself (embedded C, Python) using the appropriate FPGA-HW design (HDL). Thesis describe how to work with platform ecosystem, control and behaviour of aplications created during the proces of getting acquainted with the platform and options how aplications could be created.
|
|
|
Design of hardware cipher module
Bayer, Tomáš ; Stančík, Peter (referee) ; Sobotka, Jiří (advisor)
This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.
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