Original title: Automatizovaný testbed pro SIL/PIL testování firmware pomocí FPGA
Translated title: Automated testbed for SIL/PIL testing of embedded application using FPGA
Authors: Prusák, Lukáš ; Burian, František (referee) ; Arm, Jakub (advisor)
Document type: Master’s theses
Year: 2022
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]
Diplomová práca sa zaoberá návrhom testbench na vybraný soft-core procesor NEORV32 architektúry RISC-V pre simulácie embedded aplikácií v prostredí FPGA. Testbench bol vytvorený v prostredí Vivado s cieľom jeho rozšírenia na testovací a validačný framework. Boli vybrané a implementované základné moduly ako GPIO, PWM, UART a PC. Pre tieto moduly bolo navrhnutých niekoľko testovacích scenárov. Testbench bol tiež doplnený o pomocné skripty, pre korektné hierarchické nastavenie projektu a spúšťanie testov. Práca ďalej navrhuje aj niekoľko možných spôsobov vylepšenia a rozšírenia testbenchu. The master's thesis deals with designing a testbench for a selected soft-core processor NEORV32 with a RISC-V architecture for simulations of embedded applications in an FPGA environment. The testbench was created in the Vivado environment with the aim of extending it to a testing and validation framework. Basic modules such as GPIO, PWM, UART, and PC were selected and implemented. Several test scenarios have been designed for these modules. The testbench has also been supplemented with additional scripts, to create hierarchically correct project setup and test execution. The work also suggests a few possible ways to improve and expand the testbench.
Keywords: CPU; FPGA; HDL; NEORV32; RISC-V; soft-core; SystemVerilog; tcl; testbed; testbench; VHDL; Vivado; CPU; FPGA; HDL; NEORV32; RISC-V; soft-core; SystemVerilog; tcl; testbed; testbench; VHDL; Vivado

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/204799

Permalink: http://www.nusl.cz/ntk/nusl-502089


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses