Original title: Implementace PCS a PMA podvrstvy 50 Gb/s Ethernetu v FPGA
Translated title: FPGA implementation of PCS and PMA sublayer of 50Gb/s Ethernet
Authors: Suchanek, Michal ; Levek, Vladimír (referee) ; Bohrn, Marek (advisor)
Document type: Bachelor's theses
Year: 2019
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]
Cílem této bakalářské práce je seznámit se se standardem 25/50 Gigabit Ethernet Consortium, jenž definuje 50Gb/s Ethernet. Prostudovat specifikace pro PCS a PMA podvrstvy fyzické vrstvy Ethernetu v režimu 50GBASE-R. Podle těchto specifikací navrhnout a implementovat zmiňováné podvrstvy PCS a PMA v jazyce VHDL pro obvody FPGA na akcelerační kartu. Ověřit funkčnost fyzické vrstvy na zvolené akcelerační kartě. The main goal of this thesis is to familiarize with 25/50 Gigabit Ethernet Consortium standard, which defines 50Gb/s Ethernet. Study about PCS and PMA sublayer specifications for Ethernet physical layer in 50GBASE-R mode. Describe and implement mentioned PCS and PMA sublayers in VHDL language for FPGA circuits and selected acceleration card. Verify correct functionality of physical layer through tests on given acceleration card.
Keywords: ethernet; FPGA; physical layer; VHDL; ethernet; FPGA; fyzická vrstva; VHDL

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/173798

Permalink: http://www.nusl.cz/ntk/nusl-401390


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses