|
|
Fast Processing of Application-Layer Protocols
Bárta, Stanislav ; Martínek, Tomáš (referee) ; Polčák, Libor (advisor)
This master's thesis describes the design and implementation of system for processing application protocols in high-speed networks using the concept of Software Defined Monitoring. The proposed solution benefits from hardware accelerated network card performing pre-processing of network traffic based on the feedback from monitoring applications. The proposed system performs pre-processing and filtering of network traffic which is handed afterwards passed to application modules. Application modules process application protocols and generate metadata that describe network traffic. Pre-processing consists of parsing of network protocols up to the transport layer, TCP reassembling and forwarding packet flow only to modules that are looking for a given network traffic. The proposed system closely links intercept related information internal interception function (IRI-IIF) and content of communication internal interception function (CC-IIF) to minimize the performing of duplicate operations and increase the efficiency of the system.
|
|
|
Hardware Acceleration of Header Field Extraction
Polčák, Libor ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
Most network devices need to obtain specific packet header fields belonging to different network protocol headers for correct functionality. This work aims to create an efficient unit capable of application-specific packet header analysis and data extraction. The proposed unit deals with protocols used on L2, L3, and L4 layers of ISO/OSI model including tunneled protocols; it is possible to specify protocols which are to be supported. Data analysis is based on right linear grammar transformed to finite automaton. Hardware acceleration has to be exploited in order to achieve data processing of all traffic exchanged over high-speed networks. Using FPGA technology it is possible to achieve both fast and configurable data processing. The designed unit is able to process data on up to 40 Gbps networks. On-the-fly configuration of extracted header fields is supported.
|
|
| |
|
|
Time Synchronization in Computer Networks
Matoušek, Denis ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The master's thesis deals with design of a solution for time synchronization in computer networks that is a crucial problem of many network applications. Based on analysis of protocols for time synchronization, PTP protocol was chosen as an appropriate candidate. The thesis describes the implementation of the design for a special network interface card and demonstrates features of the solution in several tests. A part of the solution processing precise timestamps was implemented in FPGA chip on the network card while PTP messages are processed in a software application. Values of configurable parameters of the application were determined based on analysis of the network card properties and results of particular tests. It was achieved accuracy in order of tens of nanoseconds.
|
|
|
Acceleration of Open vSwitch
Vodák, David ; Orsák, Michal (referee) ; Martínek, Tomáš (advisor)
Virtual switch is a program, which is used for connecting virtual machines to network and that is why it is a crucial part of server virtualization. However virtual switch is consuming too much performance of the server which it is running on. A measurement of Open vSwitch (OvS) indicates that for data speed of 10 Gb/s, approximately 4 cores of the processor are fully occupied. As the consumption of performance is directly proportional to transmission speed, it may eventually get to the point where the consumption of performance cannot be handled. This bachelor thesis is about acceleration of the Open vSwitch with the help of the DPDK Poll Mode Driver extended by support of the SR-IOV virtualization technology as well as the interface for offloading classification rules to hardware called RTE flow. In the scope of this thesis the SR-IOV is implemented and then tested on OvS. Furthermore, the RTE flow support was designed and partially implemented.
|
|
|
Hardware Accelerating of Encryption Algorithm
Hradil, David ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
The goal of this thesis is to design a hardware realization of circuit which will implement the AES algorithm. A motivation was to make an acceleration against the classic software encryption. The acceleration is achieved by special designed parts of the circuit, which correspond to particular operations of the AES algorithm. First, there was necessary to design the circuit. In the next step there was a need to describe the designed circuit by the VHDL language. Then the circuit was simulated and synthesized. Due to comparing the circuit with software processing a software implementation was created. Both implementations were created for the FITKit platform. The hardware implementation is made by the FPGA technology and the software implementation is realized in a microcontroller. The result of the thesis is almost one thousandfold acceleration against the classic software encryption.
|
|
|
Detection of Genome Variations
Beluský, Tomáš ; Vogel, Ivan (referee) ; Martínek, Tomáš (advisor)
An influence of variations in human genome is perceptible at a first glance on human itself to see differences between the individuals and entire populations. Also, behavior or probability of certain diseases are influenced in large way by differences at genome's level. This work presents methods for detecting variations in the human genome that were developed after an arose of the second-generation sequencing technologies. A new tool that combines read pair and split read methods, with information about a depth of coverage was also designed and implemented. The tool was tested on simulated and real data and compared with a reference outputs.
|
|
|
Analysis of DNA Structure Elements
Knytl, Marek ; Burgetová, Ivana (referee) ; Martínek, Tomáš (advisor)
The aim of this master's thesis is the design and implementation of tool trackAnalysis for statistical analysis of DNA structure elements. The positions of individual elements in genome are obtained in the form of the track, and with these positions the tool performs a set of analyzes, including randomness test of track, test examining distances between track and genes, detection of clusters and overlaps. The indivudual tests results can be linked together. The results will be displayed in the form of a list, a graph or a new annotation track. An important part of this thesis is also testing the resulting tool on a set of real data.
|
|
|
Detection of Enzymes in Metagenomic Data
Smatana, Stanislav ; Martínek, Tomáš (referee) ; Hon, Jiří (advisor)
This thesis presents specification and implementation of a system for detection of enzymes in metagenomic data. The detection is based on a provided enzyme sequence and its goal is to search the metagenomic sample for its novel variants. In order to guarantee that found enzymes truly have the desired catalytic function, the system employs a number of catalytic function verification methods. Their specification, implementation and evaluation is one of the main contributions of this thesis. Experiments have shown, that proposed methods reach sensitivity as high as 89%, specificity of 95%, values of AUC metric above 0.9 and average throughput of 1,203 verifications per second on regular personal computer. Evaluation of the system also led to discovery of a partial sequence of novel haloalkane dehalogenase enzyme in a metagenomic sample from soil. The implementation is able to work on a personal computer as well as on a grid computing environment.
|
|
| |
guest ::
RSS feed.