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Parser and Validator of Data Models in YANG Language
Vican, Pavol ; Kekely, Lukáš (referee) ; Kořenek, Jan (advisor)
Computer network administrators need tools for configuration and monitoring of network devices. Therefore, NETCONF protocol was designed for remote devices configuration and YANG modelling language which describes the structure of the configuration data. The aim of this thesis is to extend the libyang library with syntax parser, that processes models written in YANG and stores them into internal structures. This parser is generated by bison and flex tools.
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Functional Verification Framework for Multi Buses Following the UVM Standard
Beneš, Tomáš ; Šišmiš, Lukáš (referee) ; Kekely, Lukáš (advisor)
This thesis focus on the design and subsequent implementation of a multi-bus verification environment using the principles of the Universal Verification Methodology (UVM). It also focus on the implementation of the verification of three FPGA components using multi-bus as input and output interfaces. The implementation of the environment and all verifications is written in SystemVerilog language using a library that implement the basic constructs for UVM. The achieved results of the work are functional and easily reusable when creating further verifications using multi-bus. The proposed environments can be used as a structure for creating other verification environments for other buses.
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DNS Service Attacks Simulation
Navrátil, Tomáš ; Kekely, Lukáš (referee) ; Kováčik, Michal (advisor)
The theme of this bachelor‘s thesis is the simulation and detection of cybernetic attacks on the DNS service. The goal was to simulate chosen attacks, analyze their behavior and create a tool capable of detecting these attacks in network traffic and replicating them for research purposes. The tool was able to successfully detect DNS attacks in normal network conditions. These results are discussed further at the conclusion of this paper, along with possible uses this application might have to other developers, and ways the program could be improved or extended in the future.
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I/O Virtualization in Networking
Perešíni, Martin ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
Existuje veľa rôznych dôvodov pre spoločnosti a organizácie, prečo by mali investovať do virtualizácie. Asi najväčší dôvod je finančná motivácia, pretože nasadenie virtualizácie môže ušetriť nemálo peňazí. Táto práca sa zaoberá práve problémom virtualizácie I/O operácií v sieťovom prostredí. Cieľom práce je tvorba softvérových ovládačov pre I/O virtualizáciu, ktoré by mohli pracovať s hardvérovo akcelerovanými sieťovými kartami. Hlavným prínosom ovládačov by mala byť použiteľnosť a čo najmenšia strata prenosového výkonu vo virtualizovanom prostredí. Pred popisom finálnych detailov ovládačov je však potrebné uviesť potrebné teoretické základy. Teoretická časť sa zaoberá súčasnými trendami vo virtualizácii I/O, technológiami ako sú virtio, vhost, SR-IOV, VFIO a mdev. V praktickej časti sú navrhuté dva spôsoby riešenia problému. Prvým je použitie technológie virtio (emulácia softvéru). Druhé je založené na technológii VFIO-mdev (hybridná paravirtualizácia). Pokiaľ sa jedná o výkon a konfigurovateľnosť zariadení, oba prístupy majú rôzne benefity. Tieto riešenia majú aj svoje nevýhody, ako je zložitosť riešenia a náročnosť integrácie do systému. Požadované ciele boli úspešne dosiahnuté vo forme prototypu ovládača nfb_mdev.
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Application Specific Processor for Stateful Network Traffic Processing
Kučera, Jan ; Matoušek, Jiří (referee) ; Kekely, Lukáš (advisor)
This bachelor's thesis deals with the design and implementation of an application-specific processor for high-speed network traffic processing. The main goal is to provide complex system for hardware acceleration of various network security and monitoring applications. The application-specific processor (hardware part of the system) is implemented on an FPGA card and has been designed with respect to be used in 100 Gbps networks. The design is based on the unique combination of high-speed hardware processing and flexible software control using a new concept called Software Defined Monitoring (SDM). The performance and throughput of the proposed system has been verified and measured.
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Implementation of Self-Correcting Codes for 100 Gb/s Ethernet
Velecký, Jan ; Kučera, Jan (referee) ; Kekely, Lukáš (advisor)
The thesis deals with the design of entire RS-FEC layer for the 100 Gb/s Ethernet according to IEEE 802.3-2015 standard including Reed-Solomon encoder and decoder. Text clarifies mathematical basis of finite fields, linear block codes, cyclic codes and particularly Reed-Solomon codes used in design. Design of RS-FEC layer transmit side has been adjusted for implementation in COMBO network cards which use Xilinx Virtex-7 FPGA and realized in VHDL. Encoder has been optimized in several steps - as for FPGA resource usage and as for VHDL code synthesis duration. Reduction of resource usage has been achieved by using pipelining thanks to properties of cyclic codes. Synthesis duration then by creating logic of encoder on gate level on its own. Resulting implementation has been tested in simulation and it is optimized enough for usage in FPGA for Ethernet implementation. It is possible to adapt both design and implementation for 400Gb/s Ethernet which does not exist yet at the time of design.
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Demonstration Examples for Pynq Z2 System on Chip Platfrom
Polášek, Patrik ; Mrázek, Vojtěch (referee) ; Kekely, Lukáš (advisor)
The thesis deals with the Pynq Z2 with SoC containing FPGA programmable logic connected to ARM processor. The main goal is to create a set of sample applications that use the peripherals available on the development board and perform critical computations on the FPGA. These applications take the form of a template dividing the functionality into a part communicating with the peripherals and another part implementing the actual computation algorithm. Specific algorithms were chosen from the areas of text search (Knuth-Morris-Pratt algorithm), image filtering (image color change and smoothing convolution mask), audio signal filtering (low pass), and internet packet classification (decision tree). The algorithms can be replaced with custom ones, while the surrounding interface for communication with the periphery is preserved. In addition to the implementation itself, an interactive Jupyter Notebook document is provided for each application with accompanying material to facilitate understanding of the subject matter.
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RISC-V Processor Peripherals
Vavro, Tomáš ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
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Accelerated Detection of Network Security Threats
Piecek, Adam ; Kekely, Lukáš (referee) ; Kučera, Jan (advisor)
This bachelor's thesis deals with the acceleration of IDS (Intrusion Detection System) for detection of security threats in networks. The main goal of the thesis is a proposal to use the Software Defined Monitoring (SDM) concept to accelerate the activity of IDS applications with a regard to their subsequent deployment for high-speed network analysis. The proposed system is implemented and subsequently evaluated for two selected open-source applications - Snort and Suricata. Over and above the task, native support for the SZE2 interface for packet acquisition is also implemented for the Suricata system in order to achieve even faster acceleration using an accelerated network interface card. Two alternatives of the concept are further analysed and compared in the thesis. The first alternative uses the hardware-accelerated version of SDM, while the second alternative is based on full software implementation of the SDM principle. Both alternatives are then evaluated in terms of achieved results and performance parameters of the entire system before and after the acceleration.
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