National Repository of Grey Literature 5 records found  Search took 0.01 seconds. 
MicroBlaze processor implementation using CodAL language
Hájek, Radek ; Zachariášová, Marcela (referee) ; Pristach, Marián (advisor)
The diploma thesis contains theoretical basis, classification and function of processors. It summarizes the principle of pipelined instruction processing and the types of hazards in the microarchitecture of the processor. It also introduces design of processors using CodAL language developed by Codasip company. In the practical part of the thesis the model of MicroBlaze core developed by Xilinx company was described in the CodAL language. Designed model was tested and implemented into the FPGA device as practical example.
Digital techniques in laboratory
Harvánek, Michal ; Mego, Roman (referee) ; Frýza, Tomáš (advisor)
The result of this project are complete proposals labs to demonstrate theoretical knowledge in the field of synchronous and asynchronous counters, state machines, combinational circuits and special hazards occurring in combinational logic functions. The project utilized educational system from RC Didactic, whose main advantage is the illustrative proof of the logic circuits and a simple computer application utilized in the analysis of digital and analog circuits. Designe tasks can be involved in a two-hour time limit labs of BICT course.
Digital techniques in laboratory
Harvánek, Michal ; Mego, Roman (referee) ; Frýza, Tomáš (advisor)
The result of this project are complete proposals labs to demonstrate theoretical knowledge in the field of synchronous and asynchronous counters, state machines, combinational circuits and special hazards occurring in combinational logic functions. The project utilized educational system from RC Didactic, whose main advantage is the illustrative proof of the logic circuits and a simple computer application utilized in the analysis of digital and analog circuits. Designe tasks can be involved in a two-hour time limit labs of BICT course.
MicroBlaze processor implementation using CodAL language
Hájek, Radek ; Zachariášová, Marcela (referee) ; Pristach, Marián (advisor)
The diploma thesis contains theoretical basis, classification and function of processors. It summarizes the principle of pipelined instruction processing and the types of hazards in the microarchitecture of the processor. It also introduces design of processors using CodAL language developed by Codasip company. In the practical part of the thesis the model of MicroBlaze core developed by Xilinx company was described in the CodAL language. Designed model was tested and implemented into the FPGA device as practical example.
Instruction Scheduler of C Compiler for Pipelined Architectures
Kocina, Filip ; Husár, Adam (referee) ; Hruška, Tomáš (advisor)
This work is engaged in the backend of a C compiler, in particular the instruction scheduler. It analyzes possibilities of the instruction scheduler in the LLVM compiler platform. It describes substitution of the current delay slot filler for MIPS architecture.

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