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A Tool for Post-Mortem Debugging
Kapičák, Peter ; Peringer, Petr (referee) ; Smrčka, Aleš (advisor)
The goal of this work is checking specific properties in trace which program should meet or which it shouldn't meet. Properties and their description are basis of this tool for post-mortem debbuging. Properties are transformed to deterministic finite automaton for checking in trace and their description is important for searching events in trace. Events are pass to automaton as input. Output of a tool is report if properties are meet or not. Solution provides check of properties regardless of log format and shows events that preceded violation of the properties.
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Design of Environment for Many-Core Systems Debugging
Klčo, Michal ; Matula, Peter (referee) ; Hynek, Jiří (advisor)
This thesis describe problem of debugging many-core systems using the integrated development environments. It presents some of the integrated environments, debuggers, their features and analyse them. This thesis also describe designs and implementation of modifications of these tools that helps user to debug many-core system more efficiently and comfortable.
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Tool for Payment Format Definition Debugging
Kuba, Richard ; Rychlý, Marek (referee) ; Zendulka, Jaroslav (advisor)
The main goal of this thesis is to develop and demonstrate a tool for debugging payment formats that would make it easier for users of the DMEEX transaction (program) to detect bugs in definition trees. Demonstration of the debugging tool is implemented on the SAP S / 4HANA platform. The first part of this thesis describes the platforms SAP R / 3 and SAP S / 4HANA, with emphasis on capturing the differences between them. Furthermore, the purpose of payment formats and their integration within SAP systems is discussed. The design describes the collection and work with user requirements for this tool. The implemented product allows users to visualize the processing of the DMEEX transaction definition tree, thanks to which it allows its users to more easily detect errors in the definition of the tree or in its input data.
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A CPU Emulator for Assembler Course
Charvát, Lukáš ; Nagy, Jan (referee) ; Smrčka, Aleš (advisor)
The bachlors's thesis discusses the design of a CPU architecture emulator aimed to assembly languages course. While most of nowadays emulators are architecture specific, this document describes an approach to create an emulator allowing users to easily set up their own architecture, to perform operations upon it, and to display its current state.
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Automated Processing of Log Files in BeeeOn System
Beňo, Marek ; Krobot, Pavel (referee) ; Vampola, Pavel (advisor)
The paper concerns with processing of log files from server applications . System architecture is based on study of availible technologies . Firstly , design of unified log format and impelementation of unified logger library is described . Secondly , installation and configuration of used technologies and their integration is described . The result is log processing system designed to be scalable in the future . System was tested and integrated into project BeeeOn .
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Simulation of an ARM Processor for the Education of Programming in Assembler
Ondryáš, Ondřej ; Goldmann, Tomáš (referee) ; Orság, Filip (advisor)
This thesis aims to implement a didactic tool for simulation of an Arm-based processor integrated into the Visual Studio Code editor. The tool facilitates learning about the machine-level programming of these processors. It implements a service that provides an assembler and a simulator for the A32 instruction set. The service is built using the Unicorn emulation framework and other open-source tools. The editor extension uses the service to add support for the development and debugging of programs written in the assembly language. It shows descriptions of used instructions and helps the programmer understand their function. When debugging, it enables stepping through the code and provides various views of the state of the simulated processor, its registers and memory. The solution can be used in the Advanced Assembly Languages course at FIT BUT. It could be further improved in the future to support other architectures and provide an easy learning environment in other courses related to machine-level programming.
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Debugging Class for php
Kluvánek, Jakub ; Krček, Petr (referee) ; Roupec, Jan (advisor)
The aim of this work is to create a tool that assists in developing and debugging PHP applications. It also provides an overview of how PHP handles errors and exceptions in a standard way. The result of this bachleor thesis is easy to use class that is easily extendable for additional functionality and contains all basic tools useful in development. This functions is nescessary because users should not view some detailed information about the error. Errors may contain sensitive information (especially passwords for the database, table structure,...). I am using this class in several projects and it seems to be very useful.
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Discrete Graph State Application Driver
Melkus, Josef ; Doležal, Jan (referee) ; Smrž, Pavel (advisor)
The aim of this work is to create a framework for integration testing of C++ systems based on their state diagrams. One part of the framework is a library defining the creation and transitions of a state diagram. Another part is an interface working on this library, that records state transitions in a run of a system. Records are then compared with an etalon. Etalon is the run of the system, that we consider as correct for a given set of inputs. The last part is an application for comparing state transitions and a script for test automation. The created system was tested within a partner company.
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Vizualization of Automata Algorithms
Kuchyňka, Jiří ; Češka, Milan (referee) ; Holík, Lukáš (advisor)
Tato práce se zabývá návrhem a implementací generického systému k vizualizaci algoritmů, které pracují nad automaty. Výsledný systém zcela odděluje část, která se věnuje generování dat k vizualizaci a část, která se věnuje vizualizování. Systém pouze určuje jejich komunikační rozhraní. Práce se zaměřuje na integraci takovéhoto systému do existujících knihoven takovým způsobem, aby byly minimalizovány požadavky na programátora, k tomu aby mohl vizualizovat stav svého algoritmu. Práce se také zkráceně věnuje možnostem využití tohoto systému k vizualizaci stavu algoritmu při krokování programem během ledění. Navržený systém může být použit pro výuku, výzkum a praktické aplikace v oblasti teorie automatů. V budoucnu by mohl být systém rozšířen o nástroje k vizualizaci turingových strojů a algoritmů pracujících nad nimi.
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Simulation of an ARM Processor for the Education of Programming in Assembler
Ondryáš, Ondřej ; Goldmann, Tomáš (referee) ; Orság, Filip (advisor)
This thesis aims to implement a didactic tool for simulation of an Arm-based processor integrated into the Visual Studio Code editor. The tool facilitates learning about the machine-level programming of these processors. It implements a service that provides an assembler and a simulator for the A32 instruction set. The service is built using the Unicorn emulation framework and other open-source tools. The editor extension uses the service to add support for the development and debugging of programs written in the assembly language. It shows descriptions of used instructions and helps the programmer understand their function. When debugging, it enables stepping through the code and provides various views of the state of the simulated processor, its registers and memory. The solution can be used in the Advanced Assembly Languages course at FIT BUT. It could be further improved in the future to support other architectures and provide an easy learning environment in other courses related to machine-level programming.
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