|
|
Multiaxis feedback cooling of particle in optical trap
Číž, Adam ; Adámek, Roman (referee) ; Brablc, Martin (advisor)
This thesis deals with a design and implementation of algorithms for multiaxis feedback cooling (which means positional control) of a particle in an optical trap with use of Kalman filter. Two control methods are proposed here, each of which is intended for use of a different actuator: a laser intensity modulator or a pair of electrodes. Next, the implementation of both methods on hardware with an FPGA is described. Functioning of both proposed algorithms is proven by a numerical simulation. In addition, the functioning of the control using electrodes is demonstrated by an experiment with an optical trap. The second method is fully prepared for use in an experiment.
|
|
|
Automated testbed for SIL/PIL testing of embedded application using FPGA
Prusák, Lukáš ; Burian, František (referee) ; Arm, Jakub (advisor)
The master's thesis deals with designing a testbench for a selected soft-core processor NEORV32 with a RISC-V architecture for simulations of embedded applications in an FPGA environment. The testbench was created in the Vivado environment with the aim of extending it to a testing and validation framework. Basic modules such as GPIO, PWM, UART, and PC were selected and implemented. Several test scenarios have been designed for these modules. The testbench has also been supplemented with additional scripts, to create hierarchically correct project setup and test execution. The work also suggests a few possible ways to improve and expand the testbench.
|
|
|
Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.
|
|
|
Optimization of supporting cryptographic operations using hardware
Čurilla, Jakub ; Smékal, David (referee) ; Cíbik, Peter (advisor)
This work deals with the description of FPGA architecture circuits, their structure, VHDL language, FPGA design flow, cryptography and cryptographic operations, and subsequent implementation and realization of support functions for cryptographic operations in VHDL language, their time and performance analysis, and mutual comparison.
|
|
|
Interface for Communication on Hardware Accelerated Circuits
Slávik, Mark ; Cíbik, Peter (referee) ; Smékal, David (advisor)
The work deals with the description and implementation of the MicroSD interface on programmable logic arrays. The thesis describes the FPGA theory, VHDL language, Vivado environment,pheripherals on FPGA board, VitisHLS. Next, the implementation of the code and its simulation is described. At the end, digital image processing using FPGA and Micro SD card is explained.
|
|
|
HDR Tone-Mapping Acceleration on Xilinx Zynq Platform
Nosko, Svetozár ; Zemčík, Pavel (referee) ; Musil, Martin (advisor)
This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.
|
|
|
Reconfigurable 5G NR signal generator on RFSoC FPGA
Indrák, Dominik ; Gazda, Juraj (referee) ; Maršálek, Roman (advisor)
This work deal with simulation of basic structure of OFDM modulator and demodulator of the upcoming standard 5G NR. In MATLAB are simulated basic parts including modulation, reference signal inserting, Fourier transform, cyclic prefix inserting, AWGN and multi-path propagation. In this work is proposed implementation of the modulator and demodulator into RFSoC board and his configuration. Designed generator is implemented with the use of STEMLab RedPitaya platform. In Matlab software is generated 5G OFDM signal used to transmitt. Received signal is evaluated in Matlab software.
|
|
|
Mixed criticalities in motor control applications on Zynq platform
Pamánek, David ; Veselý, Libor (referee) ; Blaha, Petr (advisor)
This thesis contains introduction to PMS motor control using development board ZedBoard with Xilinx Zynq-7000 SoC. After that, there is a description of development environment Vivado and other modules. Finally, it contains description or created modules in Vivado environment which were combined together with peripheral drivers to demonstrate field oriented motor control algorithm of small PMS motor.
|
|
|
Design and implementation of Twofish cipher on the FPGA network card
Cíbik, Peter ; Martinásek, Zdeněk (referee) ; Smékal, David (advisor)
This bachelor thesis deals with implementation of block cipher Twofish on the FPGA platform in VHDL language. The teoretical introduction explains basics of cryptography and symetric ciphers block operation modes, FPGA platform and introduction to VHDL language. In the next part the Twofish cipher, its components and flow are being dis- cussed in depth. Subsequently describes design of Twofish cipher in VHDL language and induvidual steps in this process. The last part deals with own implementation on hardware card with FPGA chip and summarizes reached goals.
|
|
|
FPGA based controller drive of BLDC motor
Makówka, David ; Kváš, Marek (referee) ; Valach, Soběslav (advisor)
This bachelor’s thesis concerns different control approaches for driving a BLDC motor using an FPGA chip. Also, a custom type of an inverter circuit was designed. A six-step commutation control scheme has been implemented, to ease the future integration of field-oriented control. The field-oriented control has been designed and simulated in a semestral thesis using a MATLAB Simulink tool. The targeted platform is the FPGA development board Basys 3. Hardware is rated to deliver up to 6 A of current. The handling of error conditions is mainly provided by a DRV8305 gate driver integrated circuit. Errors are also forwarded to the FPGA, for performing further actions. The structure of a controlling scheme is accustomed to the tuning of motor parameters rather than for end-users. Parameters can be set during motor operation and states of the control scheme are stepped separately. The sensing of voltages and currents is handled by an analog-digital converter.
|
guest ::
