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Verification environment for BLDC motor controller
Kalocsányi, Vít ; Kajan, Michal (referee) ; Dvořák, Vojtěch (advisor)
Tato práce se věnuje požadavku na důkladnou verifikaci při návrhu systému řízení BLDC motorů. V práci je vysvětlena funkční verifikace číslicových obvodů a univerzální verifikační metodika (UVM) a práce je zaměřena na návrh verifikačního prostředí s využitím této metodologie. Dále je v této práci vysvětlena typická struktura systému řízení BLDC motoru a definován způsob verifikace takového systému řízení. Dále je popsána implementace verifikačního prostředí a diskutovány přínosy zavedení UVM do verifikačního procesu.
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Functional Verification Framework for Multi Buses Following the UVM Standard
Beneš, Tomáš ; Šišmiš, Lukáš (referee) ; Kekely, Lukáš (advisor)
This thesis focus on the design and subsequent implementation of a multi-bus verification environment using the principles of the Universal Verification Methodology (UVM). It also focus on the implementation of the verification of three FPGA components using multi-bus as input and output interfaces. The implementation of the environment and all verifications is written in SystemVerilog language using a library that implement the basic constructs for UVM. The achieved results of the work are functional and easily reusable when creating further verifications using multi-bus. The proposed environments can be used as a structure for creating other verification environments for other buses.
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Verification of digital circuit Microcore GNSS Baseband
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the master´s thesis is to verify Acquisition Engine and Tracking Engine in the Microcore GNSS Baseband digital circuit from Honeywell. Theoretical part contains a brief introduction into the satellite position determination, basic principles of the verified blocks is given and UVM methodology is introduced. Practical part contains requirements, test cases and test procedures. The verification environment is also described. In the last part of the thesis is the verification process and it´s results.
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RISC-V Processor Peripherals
Vavro, Tomáš ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
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Automated Creation of Portable Stimuli Scenarios Using Evolutionary Algorithms
Tichý, Andrej ; Bardonek, Petr (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on the automation of scenarios creation for Portable Stimulus standard. The main goal of the work is an automatic generation of tests, which are defined as graphs for the Questa inFact tool from the Mentor company. For the automation I used an evolutionary algorithm with using a grammatical evolution. The generated scenarios are connected to the existing verification environment based on UVM methodology, then the verification of the connected component is started. Based on the achieved functional and structural coverage, the individual's fitness value is calculated and propagated into an evolutionary algorithm. At the end of the work, experiments are performed on the timer component and the contribution of the proposed evolutionary algorithm is evaluated. The proposed evolutionary algorithm is configurable by grammar and user-defined basic transactions, which allows a wide range of uses. The evolutionary algorithm managed to achieve high functional and structural coverage on the verified timer component.
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Functional Verification of Robotic System Using UVM
Krajčír, Stanislav ; Čekan, Ondřej (referee) ; Zachariášová, Marcela (advisor)
One of the currently most used approaches for verification of hardware systems is functional verification. This master thesis describes design and implementation of a verification environment using UVM (Universal Verification Methodology) methodology for verifying the correctness of the robot controller in order to eliminate functional errors and faults of its implementation. The theoretical part of the thesis describes the basic information about functional verification, methodologies for creating verification environments, the SystemVerilog language and fault tolerance methodologies. The next part of thesis focuses on the design of the verification environment, its implementation and the creation of tests used to verify the correctness of the robot controller. Results of verification are discussed and evaluated in the conclusion of this work.
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Automation of Verification Using Artificial Neural Networks
Fajčík, Martin ; Husár, Adam (referee) ; Zachariášová, Marcela (advisor)
The goal of this thesis is to analyze and to find solutions of optimization problems derived from automation of functional verification of hardware using artificial neural networks. Verification of any integrated circuit (so called Design Under Verification, DUV) using technique called coverage-driven verification and universal verification methodology (UVM) is carried out by sending stimuli inputs into DUV. The verification environment continuously monitors percentual coverage of DUV functionality given by the specification. In current context, coverage stands for measurable property of DUV, like count of verified arithemtic operations or count of executed lines of code. Based on the final coverage, it is possible to determine whether the coverage of DUV is high enough to declare DUV as verified. Otherwise, the input stimuli set needs to change in order to achieve higher coverage. Current trend is to generate this set by technique called constrained-random stimulus generation. We will practice this technique by using pseudorandom program generator (PNG). In this paper, we propose multiple solutions for following two optimization problems. First problem is ongoing modification of PNG constraints in such a way that the DUV can be verified by generated stimuli as quickly as possible. Second one is the problem of seeking the smallest set of stimuli such that this set verifies DUV. The qualities of the proposed solutions are verified on 32-bit application-specific instruction set processors (ASIPs) called Codasip uRISC and Codix Cobalt.
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Verification of Function Blocks for FPGA
Kříž, Daniel ; Smékal, David (referee) ; Jedlička, Petr (advisor)
This master thesis is devoted to the issue of verification of function blocks for FPGA. The teoritical part of thesis describes the concept of verification, verification methodologies that provide the necessary tools for testing the design, and finally discusses the issue of Ethernet and its differences from the low-latency variant. The aim of the practical part of the master thesis is based on the acquired theoretical knowledge and selected verification methodology to build a verification environment, perform a thorough verification of the low-latency physical layer of Ethernet and finally measure the latency and throughput of this circuit.
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ASIPs Intelligent Testbench Automation
Badáň, Filip ; Hynek, Jiří (referee) ; Zachariášová, Marcela (advisor)
This thesis focuses on the proposal and implementation of intelligent testbench automation for application-specific processors. The main goal of the thesis is to connect UVM verification environment with already designed genetic algorithm and to prepare this verification environment for integration into Codasip Studio development environment. The core of the final solution is modification of UVM components in verification environment and communication between the genetic algorithm and the generator of random test applications.
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Unified verification environment for digital part of automotive mixed-signal integrated circuits
Petráš, Samuel ; Dvořák, Vojtěch (referee) ; Prokop, Roman (advisor)
This thesis is concerned with unified verification environment for the verification of small designs of the digital part of integrated circuits with mixed signals. By unified verification environment is meant an environment suitable for both simulation and emulation. The first chapter describes the current verification methods of such designs. The second chapter presents the requirements that emulation places on the verification environment implemented according to the Universal Verification Methodology (UVM) and the attached implementation of proposed environment. The third chapter contains practical knowledge gained during the implementation of the unified verification environment, problems and their solutions, as well as several comparisons between simulation and emulation.
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