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Automatic Searching of Instruction Extensions for Application Processors
Češka, Martin ; Křoustek, Jakub (referee) ; Masařík, Karel (advisor)
This thesis deals with the process of automatic searching of instruction-set extensions for application-specific instruction-set processors. This process uses slightly edited ISEGEN algorithm. At first, all important terms including this algorithm are described. Then there is a detailed description of implementation of whole process in C++ programming language. At last, newly created program is considered as useful or useless based on speed-up of processor at performing of input program using found extensions.
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Logic analyzer module based on PCIe card
Juřík, Tomáš ; Macho, Tomáš (referee) ; Valach, Soběslav (advisor)
The goal of this bachelor's thesis is to implement simple FPGA-based logic analyzer connected to PCI-Express bus. Furthermore four counters are implemented to generate testing dataset. This thesis describes a fundamental priciple and use of logic analyzer. An overview of Spartan-3 PCI Express Starter Kit development board and Xilinx Spartan-3 field-programmable gate array anrchitecture is given. Stages of logic analyzer development are detailed as well.
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Communication Board for Operation of Cutting Tables Systems
Bačík, Zdenko ; Straka, Martin (referee) ; Šimek, Václav (advisor)
The thesis deals with the issue of implementing a PCI interface controller utilizing the FPGA technology. It describes the design and the implementation of a PCI communication card, which is used to control servomotors in cutting machines. In the thesis, the steps taken in designing and implementation of hardware and software parts of the communication card are discussed. The result of the thesis is a functional piece of equipment, which is to be manufactured.
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Order Book Updates Generator
Cienciala, Ondřej ; Zachariášová, Marcela (referee) ; Dvořák, Milan (advisor)
This thesis analyses messages that come from NYSE Arca and ISE exchanges and provides a description of design of stock exchange updates generator which is capable of generating constrained-random messages. It can be used for testing software that handles messages from an electronic stock exchange. Techniques of coverage-driven verification and constrained-random stimulus generation are discussed. Message generation is based on XML template and because of that the generator can be adjusted for various exchanges.
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Network traffic and cyber attacks generator on the FPGA platform
Heriban, Radoslav ; Smékal, David (referee) ; Lieskovan, Tomáš (advisor)
This thesis is focused on the most common and every day more popular threat of DoS attacks. All networks are vulnerable to this kind of attack, and with growing popularity and intensity it shouldn't be underestimated. The goal of this thesis was creating hardware accelerated generator of DoS traffic intented for testing our own networks and identifying the risks. FPGA technology is used for this task, since it has proven to be more effective way of prototyping hardware design then developing ASIC. The language used to describe desired design behavior is VHDL. Designed ICMP and UDP flood attacks are simulated in Xilinx ISE development environment. Description of problems faced before any result was reached is also included for future researchers interested in similar projects.
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Semi-Automatic Optimization Using Specialized Instructions
Mikó, Albert ; Hynek, Jiří (referee) ; Masařík, Karel (advisor)
The design of instruction sets for application specific processors is a difficult task. This thesis describes the tasks of selection, marking and creation of instruction set extensions for application specific processors. The presented semiautomatic method provides the user with a simple way to select instruction set extensions by marking a section of source code in the application. The creation of the new instruction in the modelling language itself is solved automatically. Thanks to this the user can concentrate his efforts on tasks where human ingenuity and experience can be used the most.
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OFDM demodulator implementation in FPGA
Solar, Pavel ; Urban, Josef (referee) ; Maršálek, Roman (advisor)
The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The simply model of OFDM system is made in MATLAB. Because of the implementation in FPGA is generated the behavioral description of the OFDM demodulator through the combination of the schematics description and the description in the VHDL language. The ISE development environment is used.
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Network traffic and cyber attacks generator on the FPGA platform
Heriban, Radoslav ; Smékal, David (referee) ; Lieskovan, Tomáš (advisor)
This thesis is focused on the most common and every day more popular threat of DoS attacks. All networks are vulnerable to this kind of attack, and with growing popularity and intensity it shouldn't be underestimated. The goal of this thesis was creating hardware accelerated generator of DoS traffic intented for testing our own networks and identifying the risks. FPGA technology is used for this task, since it has proven to be more effective way of prototyping hardware design then developing ASIC. The language used to describe desired design behavior is VHDL. Designed ICMP and UDP flood attacks are simulated in Xilinx ISE development environment. Description of problems faced before any result was reached is also included for future researchers interested in similar projects.
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Semi-Automatic Optimization Using Specialized Instructions
Mikó, Albert ; Hynek, Jiří (referee) ; Masařík, Karel (advisor)
The design of instruction sets for application specific processors is a difficult task. This thesis describes the tasks of selection, marking and creation of instruction set extensions for application specific processors. The presented semiautomatic method provides the user with a simple way to select instruction set extensions by marking a section of source code in the application. The creation of the new instruction in the modelling language itself is solved automatically. Thanks to this the user can concentrate his efforts on tasks where human ingenuity and experience can be used the most.
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Order Book Updates Generator
Cienciala, Ondřej ; Zachariášová, Marcela (referee) ; Dvořák, Milan (advisor)
This thesis analyses messages that come from NYSE Arca and ISE exchanges and provides a description of design of stock exchange updates generator which is capable of generating constrained-random messages. It can be used for testing software that handles messages from an electronic stock exchange. Techniques of coverage-driven verification and constrained-random stimulus generation are discussed. Message generation is based on XML template and because of that the generator can be adjusted for various exchanges.
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