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Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.
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Implementation of cryptographic algorithms on the FPGA platform
Zugárek, Adam ; Sládok, Ondřej (referee) ; Smékal, David (advisor)
This bachelor’s thesis describes methods of data encryption and author’s own implementation on FPGA. The goal of this thesis is to implement cipher on a hardware accelerated network card COMBO. In the introduction is described encryption using block ciphers. Cipher AES was chosen to implement, which is famous and most using cipher. Its detailed description is described in the first part of the thesis. In the second part is described the author’s own implementation of AES cipher in VHDL. In the next part is method of interconnecting the resulting program with a framework of the FPGA card – NetCOPE. Achieved results are in the end of this thesis. The resulting program cannot encrypt network communication. It only transforms data stored in the card, which then send to host computer.
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Postquantum cryptography on FPGA
Győri, Adam ; Jedlička, Petr (referee) ; Smékal, David (advisor)
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation, subsequent implementation of the implementation on the FPGA process system. The work describes the issue of postquantum cryptography and VHDL programming language used to describe the functionality of hardware. Furthermore, the work deals with the functional implementation and simulation of all parts of the algorithm. Specifically, these are parts, key generation, encapsulation, and decapsulation. Algorithm implementation and simulations were performed in the Vivado software simulation environment, created by Xilinx. Subsequently, the synthesis and implementation was performed and the Intellectual property block was designed, the key part of which covered the functionality of the NEXYS A7 FPGA board was not available. The last part of the work deals with the workflow algorithm for implementation on FPGA board NEXYS A7.
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Optimization of supporting cryptographic operations using hardware
Čurilla, Jakub ; Smékal, David (referee) ; Cíbik, Peter (advisor)
This work deals with the description of FPGA architecture circuits, their structure, VHDL language, FPGA design flow, cryptography and cryptographic operations, and subsequent implementation and realization of support functions for cryptographic operations in VHDL language, their time and performance analysis, and mutual comparison.
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Hardware for lightweight cryptographic implementation
Jedlička, Jakub ; Cíbik, Peter (referee) ; Smékal, David (advisor)
This bachelor thesis deals with the topic of lightweight cryptography and the implementation of a selected cipher on a field programmable gate array (FPGA). Thesis first deals with the theory, where hardware elements, general cryptography and lightweight cryptography are described with focus on the LBlock and PRESENT ciphers. It then describes the selection of a cipher type and then the selection of a particular lightweight cryptography cipher. Next the LBlock cipher is selected, implemented, and tested as a custom intellectual property (IP) block using a hardware descriptive language for very fast integrated circuits (VHDL). This block is used in the block design to implement the encryptor on the ZYBO-Z7 development board. The input and output data handling is implemented on the Zynq-7000 processing system chip, which passes the data to the programmable logic. Finally this communication and implementation is described where the operational modes used for the LBlock cipher are cipher feedback mode and output feedback mode. For these operational modes, measurements are made to determine the encryption speed of the data stored on the microSD card and the pitfalls resulting from this encryption are described.
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Interface for Communication on Hardware Accelerated Circuits
Slávik, Mark ; Cíbik, Peter (referee) ; Smékal, David (advisor)
The work deals with the description and implementation of the MicroSD interface on programmable logic arrays. The thesis describes the FPGA theory, VHDL language, Vivado environment,pheripherals on FPGA board, VitisHLS. Next, the implementation of the code and its simulation is described. At the end, digital image processing using FPGA and Micro SD card is explained.
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Client side DNSSEC deployment
Nekuža, Karel ; Smékal, David (referee) ; Martinásek, Zdeněk (advisor)
Diplomová práce se zabývá problémem přístupu koncového uživatele k odpovědím ověřeným pomocí protokolu DNSSEC. Práce posuzuje možnosti nasazení a nastavování resolveru za účelem zlepšení bezpečnosti pro koncové uživatele. V práci je navrhnuto řešení problému pro operační systém Fedora Workstation. Navrhnuté řešení je realizováno a porovnáno s již existujícím řesením.
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Asymmetric Cryptography on FPGA
Dobiáš, Patrik ; Smékal, David (referee) ; Malina, Lukáš (advisor)
This bachelor thesis deals with the analysis of existing hardware implementations of asymmetric cryptographic schemes on the FPGA platform and the then implementation of the cryptographic scheme Ed25519 on this platform. The resulting implementation is described in detail and compared with existing implementations. At the end of this work, the deployment of this implementation on the Virtex UltraScale+ FPGA is described.
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Generating of flood attacks
Hudec, David ; Hajný, Jan (referee) ; Smékal, David (advisor)
The assessment comprises of two parts, describing theory and generating of flood attacks respectively. The first part covers flood attacks' analysis, deals with their available techniques and practices, known in the area, and a computer simulation program, revealing the behavior of a contested network as well as the attacker's procedure. In the following part, data generating solutions itself are described. These are represented by two hardware programs, adapted from existing solutions, and one C# application, created by the author. The comparison of these two approaches is included, as well as are the generation results and mitigation proposal.
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