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Attack Detection by Analysis of the System's Logs
Holub, Ondřej ; Puš, Viktor (referee) ; Kaštil, Jan (advisor)
The thesis deals with the attack detection possibilities and the nonstandard behaviour. It focuses on problems with the IDS detection systems, the subsequent classification and methods which are being used for the attack detection. One part of the thesis presents the existing IDS systems and their properties which are necessary for the successful attack detection. Other parts describe methods to obtain information from the operating systems Microsoft Windows and it also analyses the theoretical methods of data abnormalities. The practical part focuses on the design and implementation of the HIDS application. The final application and its detection abilities are tested at the end of the practical part with the help of some model situations. In the conclusion, the thesis sums up the gained information and shows a possible way of the future development.
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Optimization of Crossproduct-Based Classification Algorithms
Kajan, Michal ; Kořenek, Jan (referee) ; Puš, Viktor (advisor)
This thesis deals with the packet classification problem in computer networks. It introduces packet classification along with the demands on classification algorithms. Different approaches to packet classification and several concrete examples of modern classification algorithms with their properties are described. The aim is on algorithms which can be implemented in hardware. Crossproduct-based algorithms are described in more detail whose biggest advantage is classification speed, but their disadvantage consists in great memory requirements. Several optimization methods based on state space search are presented. These optimization methods are based on reduction of original ruleset by selecting a small number of rules to associative memory. Lastly, utilization of associative memory as a flexible part of classification is illustrated together with the potential hardware implementation of such memory directly on a chip.
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Stateful Firewall for FPGA
Žižka, Martin ; Kajan, Michal (referee) ; Puš, Viktor (advisor)
This thesis describes the requirements analysis, design and implementation of stateful packet filtering to an existing stateless firewall. They also deals with testing of the implemented system. The first two chapters describe the properties NetCOPE development platform for FPGA. They also describes the principle of operation firewall, which also serves as a requirements specification for stateful firewall. Then describes the detailed design of individual modules to modify the existing firewall and the proposal for the creation of new modules. It also discusses the implementation of the proposed modules and testing for proper operation. Finally, it discuss the current state of the thesis and describes possible future expansion.
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Memory Reduction of Stateful Network Traffic Processing
Hlaváček, Martin ; Puš, Viktor (referee) ; Kořenek, Jan (advisor)
This master thesis deals with the problems of memory reduction in the stateful network traffic processing. Its goal is to explore new possibilities of memory reduction during network processing. As an introduction this thesis provides motivation and reasons for need to search new method for the memory reduction. In the following part there are theoretical analyses of NetFlow technology and two basic methods which can in principle reduce memory demands of stateful processing. Later on, there is described the design and implementation of solution which contains the application of these two methods to NetFlow architecture. The final part of this work summarizes the main properties of this solution during interaction with real data.
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Network Anomaly Detection
Pšorn, Daniel ; Puš, Viktor (referee) ; Kořenek, Jan (advisor)
This master thesis deals with detecting anomalies methods in network traffic. First of all this thesis analyzes the basic concepts of anomaly detection and already using technology. Next, there are also described in more detail three methods for anomalies search and some types of anomalies. In the second part of this thesis there is described implementation of all three methods and there are presented the results of experimentation using real data.
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Packet Classification Using FPGA Technology
Puš, Viktor ; Tobola, Jiří (referee) ; Kořenek, Jan (advisor)
This diploma thesis deals with packet classification in computer networks. The problem of packet classification is described, together with requirements for classification algorithm. Then, necessary theoretical background is introduced. Contemporary approaches to the classification are described, together with the critique of the current state of the field. The main focus of the work is the new algorithm of packet classification based on problem decomposition. Unique property of the algorithm is constant time complexity in terms of external memory accesses. Algorithm implemetation is proposed, using FPGA and one external memory. Planned prototype may achieve throughput of 64 Gbit/s in the worst case.
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Bloom Filters and Their Properties
Prokop, Tomáš ; Kajan, Michal (referee) ; Puš, Viktor (advisor)
A dissertation is engaged in a description and a construction of the Bloom filter. The inventor of this filter is Burton H. Bloom. The Bloom filter represents an efficient tool for storing elements into the universal aggregate in the form of a data structure. It processes large volume of data while filling less of store space. The data structure makes it possible to insert elements and their time after time selecting in the aggregate with zero probability of errors. Part of the dissertation is explanation of properties and usage methods of the data structure including possibility of a reduction acceptable errors. An expansion of the Bloom filter is computed Bloom filter, which allows broader usage of the data structure.
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SystemVerilog Framework for DMA Controllers Verification
Zachariášová, Marcela ; Martínek, Tomáš (referee) ; Puš, Viktor (advisor)
In contemporary hardware design, verification techniques are exploited to verify the function of hardware components as well as complex systems. This thesis deals with functional verification of DMA controllers. It describes the theoretical principles of verification using the SystemVerilog language and the principles of DMA data transfer. The design of controllers is described, with the focus on design of the verification environment and results of the verification.
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Security Issues in Content Centric Networks
Hlavatý, Martin ; Kaštil, Jan (referee) ; Puš, Viktor (advisor)
Today, computer networks are dominated by data distribution and content retrieval, but technology was created for communication between hosts. Content and service access requires mappnig between what users want and where in network it can be found. Content-centric networks separate content from its location. This thesis aims to security of Content-centric networks, looks for weak spots in its design and suggests steps for improvements of their security.
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