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Universal BLDC motor controller
Pijáček, Ondřej ; Pohl, Lukáš (referee) ; Veselý, Libor (advisor)
This thesis describes the design of universal control unit for BLDC motor powered from airplane power distribution system of 28 V capable of driving motor up to 10 A. The maximal engine power is about 250 W. Important prerequisite is possibility of driving various motor size without needs of changing wiring board using only the configuration in the auxiliary memory unit. To control different motors is enough one unit with one program without any way to interfere to the unit itself.
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Modelling of 8051 Processor
Krůpa, Tomáš ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
Computer modeling is nowadays very important part of development of almost any new product. The objective of this bachelors thesis is to develop a model of 8051 microprocessor that should enlarge a portfolio of customizable processors available for Codasip platform. The complete model is described in two levels of abstraction the instruction accurate model and the cycle accurate model. For verification of the model, ANSI C programs translated by SDCC compiler were used.
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Modification of Vocal Tracks in SW Post-Production of Music
Trkal, Tomáš ; Beran, Vítězslav (referee) ; Černocký, Jan (advisor)
This thesis describes a design and an implementation of a vocal tracks processing application. The application consists of several sub-modules representing audio processors and effects. It is implemented as a plugin created with the VST technology. The plugin provides a simple control system and an integrated database of presets which help mainly less experienced users to significantly speed up the process of processing the vocal tracks. The user evaluation shows that application is successful both in creating demos and professional mixing of music tracks.
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C Language Compiler Back-End for PicoBlaze-6
Bříza, Martin ; Ďurfina, Lukáš (referee) ; Křivka, Zbyněk (advisor)
Tato práce řeší konstrukci zadní části kompilátoru jazyka C pro soft-core procesor PicoBlaze-6 od firmy Xilinx. K řešení tohoto problému bylo zvoleno užití projektu Small Device C Compiler coby přední části překladače. Vytvořené řešení poskytuje podporu volání ukazatelů na funkce a užití struktur. Hlavním přínosem této práce je přenesení pokročilých konstrukcí jazyka C na procesor PicoBlaze.
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Emulator of Simple Processor
Kuzník, Petr ; Přikryl, Zdeněk (referee) ; Křoustek, Jakub (advisor)
Emulator will be designed as generic emulator. It should be capable of emulating versatile architectures. Each architecture will be stored in separate module implemented as dynamically linked dll libraries. Main goal is for the emulator to be generic and design its structure in a way, so that it would be possible to easily add new architecture modules and design these modules with already implemented abstractions. Primarily implemented architecture will be Commodore 64. It is a personal computer used mainly in USA during 1980s.
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Transformation from C to VHDL Language
Mecera, Martin ; Kolář, Dušan (referee) ; Masařík, Karel (advisor)
The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.
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VHDL Design of Advanced CPU
Slavík, Daniel ; Šimek, Václav (referee) ; Straka, Martin (advisor)
The goal of this project was to study pipelined processor architectures along with instruction and data cache. Chosen pipelined architecture should be designed and implemented using VHDL language. Firstly, I decided to implement the subscalar architecture first, secondly, three versions of scalar architecture. For these architectures synthesis into FPGA was done and performance of these architectures was compared on chosen algorithm. In the next part of this thesis I designed and implemented instruction and data cache logic for both architectures. However I was not able to synthetise these caches. Last chapter of this thesis deals with the superscalar architecture, which is the architecture of nowadays.
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Transformation between the Microprocessor's Description Language and the Hardware Language
Novotný, Tomáš ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.
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Simulation of the 8051 Microprocessor Architecture
Šimon, Petr ; Křoustek, Jakub (referee) ; Hruška, Tomáš (advisor)
More than 90% of processors are used in embedded systems today. Processor design for embedded systems is becoming complicated, so it should be automate as much as possible. This bachelor thesis deals with design of the microcontroller 8051. Design is created according to available documentation and ISAC language is used for model description. Results of model simulations are analyzed at the end of this thesis.
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