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Linux-Based Drivers for Embedded Systems
Kopáček, Jaroslav ; Strnadel, Josef (referee) ; Dobai, Roland (advisor)
Issues of design and writing device drivers is wide-ranging and therefore in this thesis we focus on the design of drivers for devices with field-programmable gate array (FPGA). Compared to the application-specific integrated circuit processors, where functionality is immutable, it is necessary for each new FPGA configuration to write a new driver for the required behavior. This thesis deals with the analysis of requirements and possible solutions of designing and implementation of device drivers for embedded systems based on OS Linux and the possibility of development automation. This thesis includes the design and implementation a driver generator which can generate Linux-based drivers for embedded systems. The driver generator is modular so the final driver can contain only the required functionality and no unnecessary functionality. Designed driver generator has been tested on the task of controlling light-emitting diodes which are used for diagnostics of the embedded system.
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Hardware Acceleration Demo on the Pynq Z2 Board
Vosyka, Pavel ; Kekely, Lukáš (referee) ; Kořenek, Jan (advisor)
The work deals with a hardware acceleration on the Zynq platform with Pynq technology. Three examples demonstrating hardware acceleration were designed for teaching purposes. The effort was to make examples as simple as possible to make them easy to understand. Hardware accelerators are implemented in VHDL language and driven by implemented Python application. The examples were successfully implemented and evaluated.
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Priority packet queues in FPGA
Németh, František ; Sládok, Ondřej (referee) ; Smékal, David (advisor)
Master thesis is dealing with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In theoretical part of thesis are explained different types of mechanism used for providing quality of service in communication networks. Furthermore the brief description o VHDL, FPGA and framework Netcope Development Kit is a piece of theoretical part as well. The outcome of practical part contains a design, limiting packet queues based on Tocken Bucket mechanism. Design verification was made by simulations, synthesis and real implementation on smart NIC NFB-200G2QL. All kind of verificaion results are summerized in last three chapters.
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Packet generator on the FPGA platform
Bari, Lukáš ; Blažek, Petr (referee) ; Smékal, David (advisor)
The thesis deals with the theory and design of the network traffic generator on the FPGA platform. The VHDL programming language is used for the description. The work involves getting acquainted with the development processes and design tools needed to create the overall project. It also includes familiarity with the necessary FPGA, NetCOPE and COMBO cards. Based on this information, was designed, tested and implemented packet generator project for the Combo-80G card. For implementation was used framework from NetCOPE.
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Network traffic and cyber attacks generator on the FPGA platform
Heriban, Radoslav ; Smékal, David (referee) ; Lieskovan, Tomáš (advisor)
This thesis is focused on the most common and every day more popular threat of DoS attacks. All networks are vulnerable to this kind of attack, and with growing popularity and intensity it shouldn't be underestimated. The goal of this thesis was creating hardware accelerated generator of DoS traffic intented for testing our own networks and identifying the risks. FPGA technology is used for this task, since it has proven to be more effective way of prototyping hardware design then developing ASIC. The language used to describe desired design behavior is VHDL. Designed ICMP and UDP flood attacks are simulated in Xilinx ISE development environment. Description of problems faced before any result was reached is also included for future researchers interested in similar projects.
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Implementation of software radio into FPGA
Šrámek, Petr ; Maršálek, Roman (referee) ; Prokeš, Aleš (advisor)
The common objective of this project is implementation of software defined radio (SDR) into FPGA. The text contains review and comparison of several hardware concepts intended for SDRs implementation then the methods for digital implementation of various components of radios as the filters, mixers and others are mentioned. Part of the text introduces used hardware platform and describes software support for designing, simulations and implementation into hardware. Significant part of project describes complex of external hardware components as filter, amplifier and control panel designed and built within the project realization. But the main part of project demonstrates design of the software solution of radio receiver. There is specified architecture of radio for FM broadcast receiving, next the more complex systems with carrier recovery algorithm are presented. These systems are able to work with AM, BPSK and QPSK modulations. It is possible to implement all these receivers into hardware and verify their operation. The practical laboratory theme has been outlined within the project run.
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Control of Embedded System Through Internet
Dvořák, Tomáš ; Košař, Vlastimil (referee) ; Dobai, Roland (advisor)
This bachelor's thesis deals with the process of designining individual parts of system for control of embedded system based on Xilinx Zynq over the Internet. Alternative solutions are provided in each section. The thesis points out to the modularity, simplicity and extensibility of the final implementation. The thesis describes 2 implementations of such systems to demonstrate the independence of the final server and web application on the hardware platform. The first system is capable of controling the LEDs and switches on the board, while the other systém can also control the embedded display. The thesis analyzes the individual stages of the solution from the design of the hardware platform, through the operating system, the server application to the web application. The conclusion of the thesis is devoted to testing and verification of the functionality of both implemented systems.
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High speed acquisition system
Svoboda, Tomáš ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.
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Partial reconfiguration methods based on programmable structures
Kolář, Jan ; Kváš, Marek (referee) ; Valach, Soběslav (advisor)
This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.
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