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Compilation of OpenCL Applications for Embedded Systems
Šnobl, Pavel ; Čekan, Ondřej (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for programming heterogeneous systems comprising processors, graphic accelerators and other computing devices. But it also finds usage on systems composed of just one computing unit, where it allows to write parallel programs (task and data parallelism) and work with hierarchical system of memories. In this thesis, various available open source OpenCL implementations are compared and one selected is then integrated into LLVM compiler infrastructure. This compiler is generated as a part of toolchain provided by application specific instruction set architecture processor developement environment called Codasip Studio. Designed and implemented are also optimizations for architectures with SIMD instructions and VLIW architectures. The result is tested and demonstrated on a set of testing applications.
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C Compiler for VLIW Architectures
Mináč, Tomáš ; Husár, Adam (referee) ; Masařík, Karel (advisor)
This work discusses about CodAl language and Codasip framework. It describes LLVM compiling platform, LLVM IR and its possible optimizations. The result of this work is creation and implementation a proposal of global scheduling dependence on profile as extension in LLVM.
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Generation of Object Files for RISC-V
Benna, Filip ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This master’s thesis deals with the topic of program source code compilation for RISC-V processor architecture. The generated object files need to be compatible with GNU binutils open source tools which are already available for the architecture. The focus is on relocations which must be correctly detected in Codasip Studio tools and transformed into RISC-V platform specific relocation types.
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NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
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Hardware Accelerated Functional Verification of Processor
Funiak, Martin ; Kajan, Michal (referee) ; Zachariášová, Marcela (advisor)
Functional verification belongs among the current verification approaches. Functional verification checks the correctness of the implementation of the system, due to its specification. The weakness of the functional verification approach is time consumption caused by slow software simulation of implicitly parallel hardware systems. This paper presents a solution for using a hardware accelerated functional verification of the processor. The introductory chapters form the theoretical basis for the following chapters, that include a choice of solutions, an analysis, a design of a verification environment and implementation details. The conclusion includes tests of the final product, evaluation of the results and the future work perspectives.
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Modelling of PowerPC Processor
Blaha, Hynek ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Processor architectures are becoming increasingly complex, so great emphasis is put on the automation of their desings. This bachelor thesis describes the design of the PowerPC processor architecture in Codal language. The model is created according to avaliable documentation. The functionality and efficiency of the model was verified by tests provided by research group Lissom and compared to current competitor.
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Processor Models Creation Using ADL Language
Steinhauser, Dominik ; Hynek, Jiří (referee) ; Hruška, Tomáš (advisor)
Goal of this bachelor thesis is to create instruction level models of two processors Tensilica Xtensa and Sparc Leon. Models were implemented in CodAL language. Development, simulation and testing took place in Codasip Studio, an IDE developed by Codasip company. Application Specific Instruction-Set Processors can be implemented from scratch or already implemented processor can be modified to meet needs of specific aplication. My models will be added to portfolio of Codasip company to be used and modified by the user of Codasip Studio. Result of this work are tested models of these two processors. Simulator, assembler and C language compiler of these processors can be generated. Models were compared by several Benchmark tests and results were analyzed.
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RISC-V Model Creation
Nosterský, Milan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.
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Software Debugging in Codasip Studio Using JTAG Interface Simulated in RTL Simulator
Michl, Kamil ; Husár, Adam (referee) ; Zachariášová, Marcela (advisor)
This thesis is dealing with an option to connect the RTL simulation of a processor with a software debugger. Acording to my design, the communication between these components is handled using the JTAG and the Nexus interface. The simulation is controlled by a selected interface between hardware and software description languages. For the implementation, following components are used: JTAG adapter created by Codasip, RTL simulator Questa Advanced Simulator created by Mentor, a Siemens Business, and VPI interface for communication between Verilog and C++ languages. Concept presented in this thesis can be used on other implementations that depend on different programs and interfaces. The implementation contained in this thesis was tested and is fully functional. Nowadays, it is used by Codasip company and it will probably be updated and enhanced in the future.
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Transformation of a Processor Description in CodAL to SystemC Structures
Ondruš, Tomáš ; Hynek, Jiří (referee) ; Přikryl, Zdeněk (advisor)
The goal of this thesis is to create a generator of simulators and hardware representation of application specific processors in a SystemC language. An aim of the first part is to create a wrapper layer compatible with SystemC TLM 2.0 that wraps an existing simulator to avail modeling of transaction oriented systems. The second part is a generator of a hardware representation for the processor that is suitable not only for logical synthesis, but also for the simulation on a cycle accurate level. A final result is a state of the art solution comparable to existing generators.
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