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CodAL Language Editor in Eclipse Framework
Hynek, Jiří ; Dolíhal, Luděk (referee) ; Přikryl, Zdeněk (advisor)
The Master thesis is focused on creation of an editor of CodAL language for the development toolkit of the project Lissom which is based on Eclipse framework. The goal of this thesis is to analyze the problem of editor creation and the features in existing editors which add some value to their usability. The outline of parser creation and subsequent code analysis of the source codes written into the editor is described in the theoretical part. It also explains the syntax and semantic aspects of the CodAL language. In the practical part the new CodAL language editor is designed and developed. The new CodAL language editor integrated into the development toolkit of the project Lissom is the final outcome of this thesis.
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Modelling of PowerPC Processor
Blaha, Hynek ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Processor architectures are becoming increasingly complex, so great emphasis is put on the automation of their desings. This bachelor thesis describes the design of the PowerPC processor architecture in Codal language. The model is created according to avaliable documentation. The functionality and efficiency of the model was verified by tests provided by research group Lissom and compared to current competitor.
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Testing of generated C compilers for processors in embedded systems
Dolíhal, Luděk ; Kubátová, Hana (referee) ; Vojnar, Tomáš (referee) ; Hruška, Tomáš (advisor)
Vestavěné systémy se staly nepostradatelnými pro náš každodenní život. Jsou to obvykle úzce zaměřená, vysoce optimalizovaná, jednoúčelová zařízení. Jádro vestavěných zařízení obvykle tvoří jeden nebo více aplikačně specifických instrukčních procesorů. Tato disertační práce se zaměřuje na problematiku testování nástrojú pro návrh aplikačně specifických procesorů a následně i samotných aplikačne specifických procesorů. Snahou bylo vytvořit systém, ve kterém bude možné otestovat jednotlivé nástroje, jako například překladač, assembler, disassembler, debugger. Nicméně vyvstává také potřeba provádět složitější testy, například integrační, které zaručí, že mezi jednotlivými nástroji nevzniká nekompatibilita. Autor vytvořil s podporou přůběžně integračního serveru prostředí, které napomáhá odhalování a odstraňování chyb při návrhu aplikačně specifických procesorů a které je navíc do značné míry automatizované.
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Assertion-Based Verification of ASIP
Šulek, Jakub ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This thesis introduces the concept of assertion-based verifi cation of application-specifi c instruction set processors (ASIPs). The proposed design is implemented in SystemVerilog Assertions language as a part of veri fication environment created using Codasip Framework. The implemented concept is simulated in QuestaSim tool using model of Codix RISC processor. Main outcome of this thesis is the verifi cation concept usable not only on other processors, but as a part of system that automates the processor design as well.
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Virtual Machine Management System
Skála, Milan ; Zachariášová, Marcela (referee) ; Dolíhal, Luděk (advisor)
This thesis focuses on design and implementation of the application for remote management of virtual machines that will be able to manage the virtual machines automatically. It describes a motivation for deployment of virtualization technology in companies and corporations, various virtualization methods altogether with their assessment from the practical point of view. The existing, globally widespread solutions, are also analyzes in the thesis. The application, which will be able to remotely control virtual machines, is designed and implemented in the practical part of this thesis. The final part describes possibilities of further extensions of the application.
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NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
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Build Parallelization in Jenkins Environmnent
Lukášová, Michaela ; Zachariášová, Marcela (referee) ; Dolíhal, Luděk (advisor)
The goal of this bachelor's thesis is parallelization of building Codasip Studio, highly automated developement environment. It focuses on parallelization in Jenkins environment. The implemented solution is mainly focused on speeding up the actual build process. The solution uses a number of Jenkins plugins and several shell scripts, which ensures start of compilation, installation or creation of the final package.
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RISC-V Processor Model
Barták, Jiří ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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