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Code Analysis and Transformation
Křoustek, Jakub ; Masařík, Karel (referee) ; Meduna, Alexandr (advisor)
This paper describes methods and procedures used for code analysis and transformation. It contains basic information of a science discipline called reverse engineering and its use in information technologies. The primary objective is a construction of tool that can disassemble from binary form to symbolic machine code. This operation is highly dependent on the concrete instruction set, and it has to be used for a beforehand known processor architecture. This problem is solved with patterns, plug-ins, and modularity of disassembler. These features provide users the ability to add new instruction sets into this disassembler. The output is the text representation of instructions and is functionally equivalent to the in-put. The thesis demonstrates usual methods of disassembly as well as the methods made by the author.
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Information System for Software Licences
Nejedlý, Jakub ; Masařík, Karel (referee) ; Burget, Radek (advisor)
This work treats the creation of an information system for software license management. The ordering company is Codasip, which deals with processor manufacturing and creation of related software tools. This company has been using its web portal and licenses management system is its expanding module. That is why the source code of the project is written, as well as the original web interface, in PHP language, using the Nette Framework. Moreover there is the LM-X technology of software licensig described here and so the deployment in a rival solution. The specifications of the product by X-Formation and Codasip's requirements are setting the basics for license system design. The design itself and the description of the implementation according to MVP design pattern, are part of this work.
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AVR32 Model Coreation
Sarčák, Rostislav ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
This barchelor's thesis describe creation of AVR32 processor instruction-accurate model using CodAL language. In this thesis RISC AVR32 architecture, approach to implementation of the model, testing and generating of software toolchain is described. Model development is realized in Codasip framework. Model contains implementation of AVR32 instruction set. The result of this work is AVR32 processor instruction-accurate model.
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Debugging Information in Linker
Nikl, Vojtěch ; Křoustek, Jakub (referee) ; Masařík, Karel (advisor)
This thesis describes the conversion between the CCOFF object file format and the ELF file format. We start with a general object file format and its debbuging information, then we focus closely on the ELF, CCOFF and DWARF debugging information. The functionality of the CCOFF format is encapsulated in the ObjectFile class library. Then follows the description of creating an ELF object file, its filling with the proper data and its conversion back to the CCOFF format.
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Process Inspector Tool Functionality Extension
Opršal, Martin ; Masařík, Karel (referee) ; Kreslíková, Jitka (advisor)
This master's thesis deals with process management, especially the general principles that lead to improvements in company processes. It's looking for methods to facilitate the identification and description processes. There are those applications that have just the identification and description of the process easier. Following is a description of the practical implementation of this application to Microsoft SharePoint.
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Software Pipelining in the LLVM Compiler
Glasnák, Ondrej ; Hynek, Jiří (referee) ; Masařík, Karel (advisor)
This thesis discusses a design and implementation of the Software Pipelining, a optimization technique of loops in a program, which tries to exploit instruction-level parallelism. It is achieved by scheduling instructions in a way to overlap iterations of the loop and therefore execute them in a pipeline. This way optimization speeds up the final program. There is a detailed description of design and implementation of Swing Modulo Scheduling algorithm, an effective and efficient method for finding near-optimal plans for software-pipelined loops. This work has been done as a part of a larger project, the development of Codasip Framework. Part of this framework is the retargetable C compiler based on compiler architecture LLVM, in which this work is implemented.
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Syntax-Directed Editor
Šuška, Boris ; Masařík, Karel (referee) ; Kolář, Dušan (advisor)
This thesis is dealing with integration of available lexical analyzer generator tools and presents concept of parallel syntax analysis based on block-oriented syntax analysis. Results will be used during development of syntax-directed editor under Eclipse platform latter.
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Implementation of General Disassembler
Přikryl, Zdeněk ; Masařík, Karel (referee) ; Lukáš, Roman (advisor)
This thesis presents the process of creating disassembler for new designed processors. We demand automatic generation of the disassembler. Instruction set for processor is modeled by specialized language ISAC, which offers resources for description of the instruction set. For example it describes format of instruction in the assembly language or format of instruction in the binary form or behavior of this instruction. Internal model is coupled finite automata, which describes relation of textual form of the instruction and binary form of the instruction in formal way. The code of disassembler is generated from the internal model. This disassembler accepts program in binary code at the input and generate equivalent program in assembly language at the output.
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Functional Verification of Processor Execution Units
Valach, Lukáš ; Lengál, Ondřej (referee) ; Masařík, Karel (advisor)
The thesis deals with integration of functional verification into the design cycle of execution units in a hardware-software co-design environment of the Codasip system. The aim of the thesis is to design and implement a verification environment in SystemVerilog in order to verify automatically generated hardware representation of the execution units. In the introduction, advantages and basic methods of functional verification and principles of the Codasip system are discussed. Next chapters describe the process of design and implementation of the verification environment of arithmetic-logic unit as well as the analysis of the results of verification. In the end, a review of accomplished goals and the suggestions for future development of the verification environment are made.
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