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Implementation of fixed-point arithmetic unit in FPGA
Kalocsányi, Vít ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with a design of fixed-point arithmetic unit for FPGA circuits and its model in Matlab. The thesis explains a number representation in digital circuits and both basic and selected additional arithmetic operations with fixed-point numbers. The arithmetic unit’s model is designed in Matlab, the realization of the unit in VHDL is described and its implementation into FPGA is carried out. A specific example of use of designed arithmetic unit’s model for simulation of complex systems in Simulink environment is shown at the end of the thesis.
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Acceleration unit for HTTP headers identification in FPGA
Bryndza, Ivan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
The bachelor thesis deals with hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. The goal is to design and implement a hardware architecture which will be used for detection of HTTP header in packet, and to achieve the throughput needed for monitoring of 100 Gbps networks. Nondeterministic finite automata and massive parallelism has been used for pattern match detection.
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SpaceWire Endpoint implementation
Hráček, Marek ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This work deals with the SpaceWire standard, that is used to convey the communication between modules and subsystems on board spacecrafts. Theoretical part describes standard, the way it operates and logic layers in which various functions are divided. Next part is describing design of SpaceWire endpoint itself. Presented are individual components and solutions to implement features of standard. Last chapter deals with device utilization and reached speed after synthesis with specific FPGA.
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An Automated Hothouse for Young Orchid Plants
Chovančíková, Lucie ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
Constriction of automated greenhouse that shall secure ideal conditions for orchids in greenhouse (e.g. humidity, temperature, watering, air circulation etc.) is objective of this work. The first part deals with the analysis of current solutions whether commercial or professional. The second part of work describes greenhouse generally, there are technical parameters, purpose and function of single components. The third part of work occupies with proposal and construction of hardware, the fourth part occupies with description of VHDL specification. We can find out in two final part how greenhouse was construct and how it is possible to have control over greenhouse.
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Implementation of fast serial bus on FPGA
Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
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Software for digital filter verification
Tesařík, Jan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
Diploma thesis deals with design of verification environment for analyzing systems with digital filters. Verification environment is written in SystemVerilog language and it is generated by program, which is also providing generation of input data for system of filters. Matlab environment is used for gaining the reference data. The simulation of the designed involvement with digital filters is performed by program ModelSim. The most watched parameter is functional coverage which indicates how big part of the HDL description has been tested.
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Formal verification of RISC-V processor with Questa PropCheck
Javor, Adrián ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.
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An Encoder and Decoder of an Error-correction Code for Programmable Read-only Memories
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with theory of coding, analyses current groups of error correction codes and describes features and parametres of chosen representatives of these groups. By comparing these parametres along with given criteria it choses extended Hamming code as suitable code for securing read-only-memories (ROM). For this code it choses way of realization of synthetisable modules of coder and decoder and describes their design. The work describes design of synthetizable modules of coder and decoder in VHDL. Then it explains functionality of created application which is able to generate these synthetisable modules. For verification of generated modules it creates authentication environment. Part of this environment is also model of ROM allowing writing of any error value into the memory. In the end it automatically verifies generated modules of coder and decoder with various width of input information vector.
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Proprietary communication protocol for data transfer between FPGA and PC
Beneš, David ; Pavlík, Michal (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with the design and implementation of a communication protocol which allows for data transfer between a PC and an FPGA. The designed protocol supports functions such as ´write´, ´read´ and ´write with a confirmation´ with a memory. Another supported function is autonomous transfer of telemetry data from an FPGA to a PC. Described in the theoretical part of the thesis, is the communication channel that is used for packet transfer. In the practical part are defined the packets and the protocol is implemented on PC in the form of a library and as a module on FPGA.
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