Original title: Návrh a implementace opatření proti útokům postranními kanály na platformě FPGA
Translated title: Design and implementation of countermeasures against side-channel attacks on an FPGA platform
Authors: Kuřina, Petr ; Jedlička, Petr (referee) ; Dobiáš, Patrik (advisor)
Document type: Master’s theses
Year: 2024
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]

Keywords: AES; analysis; attack; cryptanalysis; design; FPGA; Sakura-X; side channels; VHDL; AES; analýza; FPGA; kryptoanalýza; návrh; postranní kanály; Sakura-X; VHDL; útok

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: https://hdl.handle.net/11012/246105

Permalink: http://www.nusl.cz/ntk/nusl-616052


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2024-06-09, last modified 2024-06-09


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