Original title: Modelování HW designu v UGE
Translated title: Hardware Modelling in UGE
Authors: Varga, Ladislav ; Očenášek, Pavel (referee) ; Smrčka, Aleš (advisor)
Document type: Bachelor's theses
Year: 2007
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Abstract: [cze] [eng]

Keywords: diagram; diagram drawing; diagram translation into VHDL source code; dynamic link libraries; graph; hardware components; hardware design; plugin; UGE; Universal graphic editor; dynamicky linkované knižnice; graf; HW komponenty; kreslenie schém; návrh hardware; preklad schémy do kódu VHDL; UGE; Univerzálny grafický editor; zásuvný modul

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/187346

Permalink: http://www.nusl.cz/ntk/nusl-600432


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses
 Record created 2024-04-02, last modified 2024-04-03


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