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HDR Tone-Mapping Acceleration on Xilinx Zynq Platform
Nosko, Svetozár ; Zemčík, Pavel (referee) ; Musil, Martin (advisor)
This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.
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Radar Altimeter for Ultralight Aircraft
Zahradník, Jiří ; Zemčík, Pavel (referee) ; Maršík, Lukáš (advisor)
In this bachelor thesis author designs a radar altimeter. In this thesis the emphasis is placed onto modular architecture and that is why this altimeter is designed as a group of independent modules communicating through BSD sockets. Software implementation is made in C++ and for sound generator is used library PulseAudio. Next topic is multithreading safety implementation of queue and stack which was made by template class to keep simplicity and generality.
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Hardware Acceleration of Encryption Algorithms Using Xilinx Zynq Technology
Linner, Marek ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The main concern of this paper are two world standard encryption algorithms Data Encryption Standard DES (DES for short) and Advanced Encryption Standard (further mentioned as AES). For these two respective algorithms, three publicly available implementations are integrated into a benchmarking code in C programming language. The code has been executed, implementations measured with three different input block lengths and bitrate calculated for each implementation. The thesis also includes hardware implementation of both encryption algorithms DES and AES using VHDL language, simulation of the synthesised circuits and calculation of the hardware implementations' bitrate using Vivado simulator's timing reports. These measured bitrates are then compared with the bitrates of benchmarked software implementations. Paper includes all source codes of the benchmarking C program and VHDL implementation, along with program written in C# used to generate VHDL components and another C# program used for automated testing.
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Using High-Level Synthesis for ZYNQ Platform Applications
Husák, Jiří ; Drábek, Vladimír (referee) ; Fučík, Otto (advisor)
This work describes using High-Level Synthesis in image processing application. The application is for Xilinx ZYNQ platform. The source code of components for FPGA is written in C++ programming language. For High-Level Synthesis is used Xilinx Vivado HLS tool. In the application are designed and implemented Sobel filter, Median filter, Bilateral filter and architecture for AdaBoost classificator. The extension of this work is implemented the component for network traffic. The component finds the begin of the packet.
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Development of high resolution RGB camera
Madeja, Jiří ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře snímající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obrazový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a specifických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu.
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Hardware Acceleration of Encryption Algorithms Using Xilinx Zynq Technology
Linner, Marek ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The main concern of this paper are two world standard encryption algorithms Data Encryption Standard DES (DES for short) and Advanced Encryption Standard (further mentioned as AES). For these two respective algorithms, three publicly available implementations are integrated into a benchmarking code in C programming language. The code has been executed, implementations measured with three different input block lengths and bitrate calculated for each implementation. The thesis also includes hardware implementation of both encryption algorithms DES and AES using VHDL language, simulation of the synthesised circuits and calculation of the hardware implementations' bitrate using Vivado simulator's timing reports. These measured bitrates are then compared with the bitrates of benchmarked software implementations. Paper includes all source codes of the benchmarking C program and VHDL implementation, along with program written in C# used to generate VHDL components and another C# program used for automated testing.
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Radar Altimeter for Ultralight Aircraft
Zahradník, Jiří ; Zemčík, Pavel (referee) ; Maršík, Lukáš (advisor)
In this bachelor thesis author designs a radar altimeter. In this thesis the emphasis is placed onto modular architecture and that is why this altimeter is designed as a group of independent modules communicating through BSD sockets. Software implementation is made in C++ and for sound generator is used library PulseAudio. Next topic is multithreading safety implementation of queue and stack which was made by template class to keep simplicity and generality.
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Development of high resolution RGB camera
Madeja, Jiří ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře snímající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obrazový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a specifických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu.
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HDR Tone-Mapping Acceleration on Xilinx Zynq Platform
Nosko, Svetozár ; Zemčík, Pavel (referee) ; Musil, Martin (advisor)
This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.
|
|
|
Using High-Level Synthesis for ZYNQ Platform Applications
Husák, Jiří ; Drábek, Vladimír (referee) ; Fučík, Otto (advisor)
This work describes using High-Level Synthesis in image processing application. The application is for Xilinx ZYNQ platform. The source code of components for FPGA is written in C++ programming language. For High-Level Synthesis is used Xilinx Vivado HLS tool. In the application are designed and implemented Sobel filter, Median filter, Bilateral filter and architecture for AdaBoost classificator. The extension of this work is implemented the component for network traffic. The component finds the begin of the packet.
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