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Detection and Error Recovery for Syntactic Analysis
Sák, Vladimír ; Dolíhal, Luděk (referee) ; Zámečníková, Eva (advisor)
Bachelor's thesis deals with error detection and recovery for syntactic analysis. The main goal of work was to design and implement a method for error detection and recovery. The proposed method is based on the Hartmann method for error detection and error recovery. The user interface, using cross-platform framework Qt was also implemented. As a result, the application prints all of the information about errors while parsing the source code.
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Architecture Information for LLVM Compiler Optimizations
Svoboda, Jan ; Dolíhal, Luděk (referee) ; Hruška, Tomáš (advisor)
Tato práce se zabývá automatickou extrakcí informací o architektuře procesoru z jazyka CodAL. Získané informace jsou využity jako základ pro cenový model optimalizátoru překladače LLVM. V rámci práce vznikl nový systém, který vytváří cenový model, převádí jej do C++ kódu a sestavuje do dynamické knihovny. Tato knihovna je za běhu načtena překladačem a využita pro přesnější rozhodování o přínosech jednotlivých optimalizací. Výsledkem práce je průměrné 14% snížení velikosti strojového kódu programů a až 68% zlepšení výkonu generovaného kódu.
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Assertion-Based Verification of ASIP
Šulek, Jakub ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This thesis introduces the concept of assertion-based verifi cation of application-specifi c instruction set processors (ASIPs). The proposed design is implemented in SystemVerilog Assertions language as a part of veri fication environment created using Codasip Framework. The implemented concept is simulated in QuestaSim tool using model of Codix RISC processor. Main outcome of this thesis is the verifi cation concept usable not only on other processors, but as a part of system that automates the processor design as well.
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Scriptable Fight System for Turn-Based Computer Game
Kanich, Ondřej ; Dolíhal, Luděk (referee) ; Husár, Adam (advisor)
This bachelor's thesis deals with creation of fight system and artificial intelligence for it. The goal of this project is to give an opportunity for low-experienced programmers to design and implement their own artificial intelligence. The Project DrdSim is used as a platform for this thesis. Extended fight system of the Dragon's lair (Czech version of D&D) is employed as a model for created system. Artificial intelligence is implemented by DSL, special language of DrdSim platform. An approach of reactive agents is used for artificial intelligence.
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Instruction Set Completness Detection for Retargetable C Compiler Generation
Nagy, Michal ; Dolíhal, Luděk (referee) ; Hruška, Tomáš (advisor)
This thesis concerns the issue of completness detection of instruction set description for the LLVM compiler, or the ability of a compiler to generate target program for every valid source program in the appropriate high-level programming language. On the basis of regular tree grammar theory and several scietific theses that also concern this issue, formal tool for inclusion checking of two grammars. Furthermore a method for automatic extraction of the two grammars from the instruction set description has been devised, as a result of which the tool can be used for checking completeness of instruction selection. In combination with checking completeness of the legalization process of the LLVM compiler, which preceeds the instruction selection, it should be feaseable to check completeness of most compiler parts dependent on the target architecture.
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RISC-V Processor Model
Barták, Jiří ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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Compiler for EdkDSP Platform
Baručák, Robert ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Goal of this bachelor's thesis was to create a compiler system for EdkDSP platform. Two different approaches to construction of compiler system for multiprocessor platform are presented. Compiler is based on LLVM compiler infrastructure. As a result, two versions of compiler system utilising hardware capabilities of EdkDSP were created. Developed solutions have a few constraints which are discussed in this paper.
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Software Execution Acceleration Using Automatic Instruction Set Extensions
Melo, Stanislav ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
One of the important feature of application specific processors is performance. To maximize it, the processor must adapt to needs of application that it is going to perform. One of the ways to do that is to search for appropriate instructions that can be joined into one special instruction. This instruction is then implemented in hardware as a single function block. This bachelor's thesis describes problem of finding and selecting suitable candidates for instruction-set extension. It also provides brief overview of the few best known algorithms that solve this problem. Moreover the thesis deals with the single-cut algorithm and its implementation in more detail.
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Virtual Machine Management System
Skála, Milan ; Zachariášová, Marcela (referee) ; Dolíhal, Luděk (advisor)
This thesis focuses on design and implementation of the application for remote management of virtual machines that will be able to manage the virtual machines automatically. It describes a motivation for deployment of virtualization technology in companies and corporations, various virtualization methods altogether with their assessment from the practical point of view. The existing, globally widespread solutions, are also analyzes in the thesis. The application, which will be able to remotely control virtual machines, is designed and implemented in the practical part of this thesis. The final part describes possibilities of further extensions of the application.
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