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Instruction level parallelism in modern processors
Sláma, Pavel ; Levek, Vladimír (referee) ; Pristach, Marián (advisor)
Basic methodology that exploits instruction level parallelism is called pipelining and it is part of every processor for decades. The ideal pipeline increases performance and efficiency for a relatively small cost. But the real pipeline has number of limitations caused by dependencies and hazards between instructions. The aim of this thesis is to discuss techniques used to improve efficency and performance of pipelined processors, to implement selected techniques to a RISC processor model and discuss its benefits.
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NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
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A New Generation of an IPFIX Collector
Huták, Lukáš ; Žádník, Martin (referee) ; Wrona, Jan (advisor)
This master's thesis addresses processing of flow monitoring records from a point of view of an IPFIX collector. It analysis the current solution of the modular collector, which went through considerable historical development, and focuses on revealing its strengths and weaknesses. Based on acquired knowledge, a new collector is designed. The new solution, which significantly modifies individual components for processing of flow records, focuses on high throughput and adds missing functionalities. The document also compares performance of both generations and the new collector clearly dominates.
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Instruction level parallelism in modern processors
Sláma, Pavel ; Levek, Vladimír (referee) ; Pristach, Marián (advisor)
Basic methodology that exploits instruction level parallelism is called pipelining and it is part of every processor for decades. The ideal pipeline increases performance and efficiency for a relatively small cost. But the real pipeline has number of limitations caused by dependencies and hazards between instructions. The aim of this thesis is to discuss techniques used to improve efficency and performance of pipelined processors, to implement selected techniques to a RISC processor model and discuss its benefits.
|
|
|
A New Generation of an IPFIX Collector
Huták, Lukáš ; Žádník, Martin (referee) ; Wrona, Jan (advisor)
This master's thesis addresses processing of flow monitoring records from a point of view of an IPFIX collector. It analysis the current solution of the modular collector, which went through considerable historical development, and focuses on revealing its strengths and weaknesses. Based on acquired knowledge, a new collector is designed. The new solution, which significantly modifies individual components for processing of flow records, focuses on high throughput and adds missing functionalities. The document also compares performance of both generations and the new collector clearly dominates.
|
|
|
NIOS II Processor Model
Masařík, Marek ; Dolíhal, Luděk (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with the implementations of Nios II processor model in the description language processor called description CodAL. The implementation of processor is on two levels of abstraction. First level of abstraction is the instruction accurate model and second is the cycle accurate model. An important part of processor design is testing and verification which were realized on the prepared benchmark set. The resulting processor can be potentially used in real applications.
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