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Analýza paralelizovatelnosti programů na základě jejich bytecode
Brabec, Michal ; Bednárek, David (advisor) ; Ježek, Pavel (referee)
Analysis of automatic program parallelization based on bytecode There are many algorithms for automatic parallelization and this work explores the possible application of these algorithms to programs based on their bytecode or similar intermediate code. All these algorithms require the identification of independent code segments, because if two parts of code do not interfere with one another then they can be run in parallel without any danger of data corruption. Dependence testing is an extremely complicated problem and in general application, it is not algorithmically solvable. However, independences can be discovered in special cases and then they can be used as a basis for application of automatic parallelization, like the use of vector instructions. The first step is function inlining that allows the compiler to analyze the code more precisely, without unnecessary dependences caused by unknown functions. Next, it is necessary to identify all control flow constructs, like loops, and after that the compiler can attempt to locate dependences between the statements or instructions. Parallelization can be achieved only if the analysis discovered some independent parts in the code. This work is accompanied by an implementation of function inlining and code analysis for the .NET framework.
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Parallelisation of Ultrasound Simulations on Intel Xeon Phi Accelerator
Vrbenský, Andrej ; Hrbáček, Radek (referee) ; Jaroš, Jiří (advisor)
Nowadays, the simulation of ultrasound acoustic waves has a wide range of practical usage. As one of them we can name the simulation in realistic tissue media, which is successfully used in medicine. There are several software applications dedicated to perform such simulations. k-Wave is one of them. The computational difficulty of the simulation itself is very high, and this leaves a space to explore new speed-up methods. In this master's thesis, we proposed a way to speed-up the simulation based on parallelization using Intel Xeon Phi accelerator. The accelerator contains large amount of cores and an extra-wide vector unit, and therefore, is ideal for purpose of parallelization and vectorization. The implementation is using OpenMP version 4.0, which brings some new options such as explicit vectorization. Results were measured during extensive experiments.
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Water Simulation Using GPU
Hanzlíček, Jiří ; Jaroš, Jiří (referee) ; Vaverka, Filip (advisor)
The goal of this thesis is to find a suitable model of fluids, the numerical simulation of which can be realized as interactive program. This requirement leads to a solution based on highly parallel algorithm. The implementation is built not only for CPU, but also GPU in a way, that allows to compare computational performance of each device on selected model.
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Tool for Security Testing of WPA-PSK
Gancarčík, Lukáš ; Kačic, Matej (referee) ; Jurnečka, Peter (advisor)
This thesis is referring to the problems of securing a wireless network, to the possibilities of defending these networks and the implementation of the tool to test them. It discusses the usage of the nVidia CUDA technology to accelerate parallel tasks. The advantages of using this technology as well as the rise of performance compared to the results of a classic processor can also be viewed. The conclusions of the tool used on a real wireless network are reviewed in the end.
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Transformation from C to VHDL Language
Mecera, Martin ; Kolář, Dušan (referee) ; Masařík, Karel (advisor)
The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.
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