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National Repository of Grey Literature 6 records found  Search took 0.00 seconds. 
Graphical Simulator of Superscalar Processors
 Vávra, Jan ; Mrázek, Vojtěch (referee) ; Jaroš, Jiří (advisor)
Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.
Detailed record
Methodology of the Speed Optimalization of the Source Code
 Matějíček, Petr ; Šimek, Václav (referee) ; Kaštil, Jan (advisor)
This thesis desribe methodology of writing computer programs to achieve higher speed of program execution. It describe general implementation tricks and ways of writing programs for arbitary computer architecture. Below this thesis descibe selected architecture and optimalization doable on it. Part of this thesis is test of this methodology on some opensource software.
Detailed record
Design and Implementation of Mechanisms for Enhancing Performance of CPU
 Zlatohlávková, Lucie ; Sekanina, Lukáš (referee) ; Strnadel, Josef (advisor)
This masters thesis is focused on the issue of processor architecture. The ground of this project is a design of a simple processor, which is enriched by modern components in processor architecture such as pipelining, cache memory and branch prediction. The processor has been made in VHDL programming language and was simulated in ModelSim simulation tool.
Detailed record
Graphical Simulator of Superscalar Processors
 Vávra, Jan ; Mrázek, Vojtěch (referee) ; Jaroš, Jiří (advisor)
Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.
Detailed record
Design and Implementation of Mechanisms for Enhancing Performance of CPU
 Zlatohlávková, Lucie ; Sekanina, Lukáš (referee) ; Strnadel, Josef (advisor)
This masters thesis is focused on the issue of processor architecture. The ground of this project is a design of a simple processor, which is enriched by modern components in processor architecture such as pipelining, cache memory and branch prediction. The processor has been made in VHDL programming language and was simulated in ModelSim simulation tool.
Detailed record
Methodology of the Speed Optimalization of the Source Code
 Matějíček, Petr ; Šimek, Václav (referee) ; Kaštil, Jan (advisor)
This thesis desribe methodology of writing computer programs to achieve higher speed of program execution. It describe general implementation tricks and ways of writing programs for arbitary computer architecture. Below this thesis descibe selected architecture and optimalization doable on it. Part of this thesis is test of this methodology on some opensource software.
Detailed record

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