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HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
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Hardware Acceleration Using Functional Languages
Hodaňová, Andrea ; Kadlček, Filip (referee) ; Fučík, Otto (advisor)
The aim of this thesis is to research how the functional paradigm can be used for hardware acceleration with an emphasis on data-parallel tasks. The level of abstraction of the traditional hardware description languages, such as VHDL or Verilog, is becoming to low. High-level languages from the domains of software development and modeling, such as C/C++, SystemC or MATLAB, are experiencing a boom for hardware description on the algorithmic or behavioral level. Functional Languages are not so commonly used, but they outperform imperative languages in verification, the ability to capture inherent paralellism and the compactness of code. Data-parallel task are often accelerated on FPGAs, GPUs and multicore processors. In this thesis, we use a library for general-purpose GPU programs called Accelerate and extend it to produce VHDL. Accelerate is a domain-specific language embedded into Haskell with a backend for the NVIDIA CUDA platform. We use the language and its frontend, and create a new backend for high-level synthesis of circuits in VHDL.
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Lossless Data Compression for IP Networks
Pánek, Richard ; Kajan, Michal (referee) ; Korček, Pavol (advisor)
This bachelor's thesis deals with data compression methods in IP networks. The LZW compression algorithm and its history is described more in detail. This algorithm is tested on the di erent types of IP tracffic. It is shown that depending on the traffic type it is possible to reduce data to 70% of its original size. As the final implementation of the LZW algorithm is intented for use in the FPGA the results from high level synthesis (from C to VHDL language) are fi nally described.
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Acceleration of HTTTP Traffic Analysis
Budiský, Jakub ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This bachelor thesis addresses hardware accelerated analysis of HTTP, the most used protocol on the Internet. The goal is to extract substantial information from the HTTP headers and to achieve throughput needed for monitoring high-speed networks. The C language is used to create a software implementation which is then optimized for parallel environment and transformed into a hardware architecture using High Level Synthesis. Both solutions, software and hardware one, are tested on real traffic samples and their throughput is measured. Achieved results are discussed and new solution is proposed on their basis.
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High level synthesis in network applications described using P4 language
Panák, Petr ; Šťáva, Martin (referee) ; Fujcik, Lukáš (advisor)
High-level synthesis is a compelling method of designing a digital circuit. High abstraction and faster verification are advantages which aren't pressent in Register Transfer Level designing. That guarantees faster designing with lower development costs. This bachelor thesis deals with a digital design of actions, extern blocks and MI32 interface access. Each component design is described using C/C++ programming language and synthesised with Intel HLS compiler.
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P4.16 Compiler Using High Level Synthesis
Neruda, Jakub ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
The P4 language is currently a hot topic in the field of network administration due to its capability to program the functionality of network devices. This language is still in development and its last revision P416 drastically changed not only the language features and syntax, but also the underlying compiler. The CESNET association supports the development of the P4 language and thus they also need to support the new standard. This work examines possible problems tied to migration, namely issues related to translation of high-level user-defined actions into VHDL description, with the help of High-level Synthesis (HLS), instantiation of so-called extern objects and the support of atomic sections. The text discusses possible ways of interconnecting the HDL components and organisation of their memory space in order to support configuration from software at runtime. The architecture of the p4c compiler is also described, complete with code examples implementing core classes participating in the compilation process. The last part of the work showcases the usage of Vivado HLS for optimizing C++ code in order to get maximum performance from the resulting firmware.
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HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
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|
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High level synthesis in network applications described using P4 language
Panák, Petr ; Šťáva, Martin (referee) ; Fujcik, Lukáš (advisor)
High-level synthesis is a compelling method of designing a digital circuit. High abstraction and faster verification are advantages which aren't pressent in Register Transfer Level designing. That guarantees faster designing with lower development costs. This bachelor thesis deals with a digital design of actions, extern blocks and MI32 interface access. Each component design is described using C/C++ programming language and synthesised with Intel HLS compiler.
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