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Educational Application of Memory Paging
Nechvátal, Petr ; Janoušek, Vladimír (referee) ; Smrčka, Aleš (advisor)
This master's thesis deals with design and implementation of educational application forpaging. Goal of the application is to help students understand and practice some conceptsfrom paging. It will allow students to write parts of these concepts and see how their codework on visualization of simulation of memory system. Application will be implemented asa web application in HTML, CSS and JavaScript. Server, which will be taking care ofcompiling of user code will be a desktop application. This thesis mainly describes pagingand technologies which will be used for this thesis and application design. It also describesimplementations and testing of this work.
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RISC-V Model Creation
Nosterský, Milan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.
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Educational Application of Memory Paging
Nechvátal, Petr ; Janoušek, Vladimír (referee) ; Smrčka, Aleš (advisor)
This master's thesis deals with design and implementation of educational application forpaging. Goal of the application is to help students understand and practice some conceptsfrom paging. It will allow students to write parts of these concepts and see how their codework on visualization of simulation of memory system. Application will be implemented asa web application in HTML, CSS and JavaScript. Server, which will be taking care ofcompiling of user code will be a desktop application. This thesis mainly describes pagingand technologies which will be used for this thesis and application design. It also describesimplementations and testing of this work.
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|
|
RISC-V Model Creation
Nosterský, Milan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors. The practical part of thesis deals with the implementation of processor RISC-V on instruction accurate level and the model testing. The thesis also deals with the implementation of MMU, timer and analysis of the proxy kernel.
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