National Repository of Grey Literature 5 records found  Search took 0.01 seconds. 
Transformation of Processor Graphical Representation to the Architecture Description Language
Netočný, Ondřej ; Husár, Adam (referee) ; Hruška, Tomáš (advisor)
This thesis deals with conversion between graphical and text representation of processor architecture. The aim is to acquaint with both of said tools and introduce the way how the conversion is done. The introduction of EMF and GMF tools of Eclipse IDE is also included in this thesis, because the graphical representation editor is based on these tools. The end of thesis is devoted to reverse transformation possibilities, where the intelligent placing of diagram nodes is required.
Transformation between the Microprocessor's Description Language and the Hardware Language
Novotný, Tomáš ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.
Transformation of Processor Graphical Representation to the Architecture Description Language
Netočný, Ondřej ; Husár, Adam (referee) ; Hruška, Tomáš (advisor)
This thesis deals with conversion between graphical and text representation of processor architecture. The aim is to acquaint with both of said tools and introduce the way how the conversion is done. The introduction of EMF and GMF tools of Eclipse IDE is also included in this thesis, because the graphical representation editor is based on these tools. The end of thesis is devoted to reverse transformation possibilities, where the intelligent placing of diagram nodes is required.
Transformation from C to VHDL Language
Mecera, Martin ; Kolář, Dušan (referee) ; Masařík, Karel (advisor)
The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.
Transformation between the Microprocessor's Description Language and the Hardware Language
Novotný, Tomáš ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.

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