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Cryptographic schemes implementation on small FPGA platforms
Pukšová, Ráchel ; Cíbik, Peter (referee) ; Dobiáš, Patrik (advisor)
The objective of the bachelor thesis is to implement the AES-GCM encryption algorithm on a Nexys A7-100T FPGA board. It introduces the issues of cryptography and authentication in data transmission as well as describes the FPGA technology. The implementation has been done in VHDL, as a hardware description language. It analyses the project provided by the Institute of Telecommunications of Brno University of Technology, which is intended to be modified to achieve the stated goal. In the practical part, it discusses the modifications made and the tests that verified the functionality of the implementation. It compares resource utilization with the original project as a tool to better understand the impact of the modifications made. This work is also compared with existing AES-GCM solutions. Finally, suggestions are given for further modifications that could be made to achieve lower goals.
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High-speed data transfer
Šimík, Jakub ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This work deals with the design of a device for sending data from a fast ADC converter to a computer via an Ethernet interface using the MicroZed 7020 development board and the Zynq 7000 system on chip that this board is equipped with. This development board and the Zynq 7000 are first presented in the work, followed by a brief description of the selected protocols, and based on a theoretical analysis, the design of the solution architecture is then carried out. The next part of the work then deals with the implementation of the device in programmable logic and software for the processing system according to the design architecture. The conclusion of the work is dedicated to verifying the correct function of individual parts of the device.
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Electronic Chessboard on the FITKit Platform
Kubín, Jakub ; Zachariášová, Marcela (referee) ; Kaštil, Jan (advisor)
This thesis deals with the analysis, design and implementation of chess on FITkit platform. The platform is connected to the VGA monitor, on which is shown the chessboard with the figures. The game is controlled by using the keyboard on FITkit platform. The work describes the realisation of the unit for the display of the checkerboard that is implemented in the programmable gate field. Software of the microcontroller controls the depictive unit, generates possible moves and checks strokes of figures. There is a control whether the King does not have the check and if the game is not over because of checkmate or stalemate.
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FPGA controller for LED video display
Dolejší, Miloš ; Bečková, Zuzana (referee) ; Hanák, Pavel (advisor)
This thesis deals with controlling a color graphic LED display using an FPGA. The first half of the theoretical part of this paper describes the properties of the used FPGA, the data source and a principle of controlling an RGB LED display. The second half describes an implementation of pulse width modulation and binary code modulation which enables the control of brightness of the display and of color depth of every sub-pixel. The practical part on the other hand describes the designing and the implementation of this module in the VHDL language. Then it explains the transfer of image data from Blackfin processor to the memory via PPI interface, the subsequent process of reading data from the memory, conversion of the data to a serial format and finally it describes the process of sending the data to the LED controller. The module was realized on the Digilent Atlys development board equipped with the Spartan-6 FPGA and was tested on a 32x20 light panel for the firm Ing. Ivo Herman, CSc.
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Acceleration unit for HTTP headers identification in FPGA
Bryndza, Ivan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
The bachelor thesis deals with hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. The goal is to design and implement a hardware architecture which will be used for detection of HTTP header in packet, and to achieve the throughput needed for monitoring of 100 Gbps networks. Nondeterministic finite automata and massive parallelism has been used for pattern match detection.
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FPGA controller for LED video display
Dolejší, Miloš ; Bečková, Zuzana (referee) ; Hanák, Pavel (advisor)
This thesis deals with controlling a color graphic LED display using an FPGA. The first half of the theoretical part of this paper describes the properties of the used FPGA, the data source and a principle of controlling an RGB LED display. The second half describes an implementation of pulse width modulation and binary code modulation which enables the control of brightness of the display and of color depth of every sub-pixel. The practical part on the other hand describes the designing and the implementation of this module in the VHDL language. Then it explains the transfer of image data from Blackfin processor to the memory via PPI interface, the subsequent process of reading data from the memory, conversion of the data to a serial format and finally it describes the process of sending the data to the LED controller. The module was realized on the Digilent Atlys development board equipped with the Spartan-6 FPGA and was tested on a 32x20 light panel for the firm Ing. Ivo Herman, CSc.
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Acceleration unit for HTTP headers identification in FPGA
Bryndza, Ivan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
The bachelor thesis deals with hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. The goal is to design and implement a hardware architecture which will be used for detection of HTTP header in packet, and to achieve the throughput needed for monitoring of 100 Gbps networks. Nondeterministic finite automata and massive parallelism has been used for pattern match detection.
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Electronic Chessboard on the FITKit Platform
Kubín, Jakub ; Zachariášová, Marcela (referee) ; Kaštil, Jan (advisor)
This thesis deals with the analysis, design and implementation of chess on FITkit platform. The platform is connected to the VGA monitor, on which is shown the chessboard with the figures. The game is controlled by using the keyboard on FITkit platform. The work describes the realisation of the unit for the display of the checkerboard that is implemented in the programmable gate field. Software of the microcontroller controls the depictive unit, generates possible moves and checks strokes of figures. There is a control whether the King does not have the check and if the game is not over because of checkmate or stalemate.
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Acceleration Unit for HTTP Headers Identification in FPGA
Bryndza, Ivan
This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP header in each packet. Architecture will be able to achieve the throughput needed for monitoring of 100 Gb/s networks. Nondeterministic finite automata and massive parallelism is used for pattern match.
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