Original title: Acceleration Unit for HTTP Headers Identification in FPGA
Authors: Bryndza, Ivan
Document type: Papers
Language: cze
Publisher: Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract: This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP header in each packet. Architecture will be able to achieve the throughput needed for monitoring of 100 Gb/s networks. Nondeterministic finite automata and massive parallelism is used for pattern match.
Keywords: BRAM; Field Programmable Gate Array (FPGA); HTTP; Nondeterministic Finite Automata (NFA)
Host item entry: Proceedings of the 21st Conference STUDENT EEICT 2015, ISBN 978-80-214-5148-3

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/42922

Permalink: http://www.nusl.cz/ntk/nusl-220452


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