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FFT implementation in FPGA and ASIC
Dvořák, Vojtěch ; Bohrn, Marek (referee) ; Fujcik, Lukáš (advisor)
The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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Implementation of modular arithmetic in FPGAs and ASICs
Sýkora, Michal ; Bohrn, Marek (referee) ; Dvořák, Vojtěch (advisor)
This thesis is focused on analysis, design and implementation of modular arithmetic in FPGAs and ASICs. Its main objective is to create a C++/SystemC library, that contains synthesizable functions for operations with Montgomery reduction in modular arithmetic. Results of the implementation of Montgomery reduction are compared with results of classic algorithms for modular arithmetic.
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Design and realization of mathematical operations in FPGA circuits
Soukup, Luděk ; Šteffan, Pavel (referee) ; Fujcik, Lukáš (advisor)
This bachelor’s thesis deals with the issue of realization of mathematical operations in digital circuits with a focus on FPGA and ASIC architectures. The attention is focused to algorithms for addition, subtraction, multiplication and division, further to algorithms for computing trigonometric functions. Chosen algorithms are described in VHDL language, synthesized, and they are compared in terms of acquired information about computing time and area which is required for its realization. In the final part of the thesis the possibility of implementation these algorithms is discussed.
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Implementation of 8-bit microprocessor into FPGA chip
Walletzký, Ondřej ; Dvořák, Vojtěch (referee) ; Bohrn, Marek (advisor)
This thesis deals with design of microprocessor compatible with one of 8-bit microcontrollers manufactured by Microchip company. Theoretical part of this thesis analyzes architectures of 8-bit PIC microcontrollers, picks one of these microcontrollers and describes its architecture and function of its subcircuits. Practical part deals with design of architecture compatible in terms of instruction execution, internal data flow and subcircuit behavior, all this to achieve the best possible program portability from target microcontroller. The last part of thesis describes method of processor implementation into FPGA chip and mentions potential design differences for ASIC implementation. It also deals with verification and method of programming.
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Modelling and simulation of analog circuits in FPGA
Kotulič, Dominik ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
Bachelor thesis is focused on seeking a suitable calculation algorithm of an exponential function which could be suitably implemented in ASIC and FPGA circuits. The first part of the thesis is aimed at brief clarifying of the issue of transients in accumulation circuits and their modelling in the program PSpice. The second part deals with seeking ways of model proposals of the exponential function appropriate for the implementation in ASIC and FPGA circuits. Subsequently, in the final part of the thesis we designed and tested two calculation algorithms of the model of the exponential function that are implemented for floating point numbers.
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Network traffic and cyber attacks generator on the FPGA platform
Heriban, Radoslav ; Smékal, David (referee) ; Lieskovan, Tomáš (advisor)
This thesis is focused on the most common and every day more popular threat of DoS attacks. All networks are vulnerable to this kind of attack, and with growing popularity and intensity it shouldn't be underestimated. The goal of this thesis was creating hardware accelerated generator of DoS traffic intented for testing our own networks and identifying the risks. FPGA technology is used for this task, since it has proven to be more effective way of prototyping hardware design then developing ASIC. The language used to describe desired design behavior is VHDL. Designed ICMP and UDP flood attacks are simulated in Xilinx ISE development environment. Description of problems faced before any result was reached is also included for future researchers interested in similar projects.
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USB communication protocol analysis
Zošiak, Dušan ; Fujcik, Lukáš (referee) ; Šteffan, Pavel (advisor)
Tato práce je zaměřena na zpracování a analýzu USB komunikačního protokolu a implementace jeho jednotlivých částí do FPGA obvodu s využitím programovacího jazyka VHDL. Ve finální podobě by měla práce představovat souhrnný a ucelený dokument popisující principy USB rozhraní a jeho komunikace doplněných praktickým návrhem v jazyce VHDL, který by byl schopen převést data do USB.
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Tests of integrated analog multipliers
Stolařová, Hana ; Dvořák, Radek (referee) ; Šotner, Roman (advisor)
This diploma thesis deals with the design of testing device (tester) for basic verification of parameters and construction of applications using analog multipliers fabricated in TSMC 0.18 m 1.8 V process. The tester is than used for several eperimental measurements such as AC responses, DC responses, total harmonic distortion, offset and input and output impedance. A part of the thesis covers also designs of application examples (circuits) wich use these special analog multipliers (triangular and square wave generator, 2nd order active filter, integrator, etc.).
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