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Hardware Accelerated Functional Verification of Processor
Funiak, Martin ; Kajan, Michal (referee) ; Zachariášová, Marcela (advisor)
Functional verification belongs among the current verification approaches. Functional verification checks the correctness of the implementation of the system, due to its specification. The weakness of the functional verification approach is time consumption caused by slow software simulation of implicitly parallel hardware systems. This paper presents a solution for using a hardware accelerated functional verification of the processor. The introductory chapters form the theoretical basis for the following chapters, that include a choice of solutions, an analysis, a design of a verification environment and implementation details. The conclusion includes tests of the final product, evaluation of the results and the future work perspectives.
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Questa Capabilities Demonstration Set
Krajčír, Stanislav ; Kajan, Michal (referee) ; Zachariášová, Marcela (advisor)
This bachelor thesis deals with presentation of capabilities of verification platform Questa Static from Mentor Graphics company. The basic information about the principles of assertion based verification is provided in the beginning. The thesis describes Questa AutoCheck verification tool which is used for automatic verification of integrated circuits and Questa Formal verification tool which is used for static formal verification of integrated circuits. The set of examples is given to demonstrate various options of using these tools for verification of a concrete integrated circuit design. In conclusion, the thesis evaluates the possibilities of application of these tools in verification process.
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Hardware Accelerated Functional Verification
Zachariášová, Marcela ; Kotásek, Zdeněk (referee) ; Kajan, Michal (advisor)
Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.
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VHDL Design of Robot Controller for Autonomous Robot Movement in Maze
Podivínský, Jakub ; Strnadel, Josef (referee) ; Zachariášová, Marcela (advisor)
This master thesis describes design and implementation of a robot controller for autonomous movement in a maze. Robot represents an exemplary system, which is designed for testing and validation of fault-tolerance methodologies. A part of this work contains introduction to reliability of digital systems, especially those which are based on Field Programmable Gate Array (FPGA). Moreover, this introduces techniques that ensure robustness against faults in digital systems; attention is devoted to the usage of FPGA technology in this area and a technique called partial dynamic reconfiguration.
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Application of Evolutionary Algorithm in Creation of Regression Tests
Belešová, Michaela ; Kajan, Michal (referee) ; Zachariášová, Marcela (advisor)
This master thesis deals with application of an evolutionary algorithm in the creation of regression tests. In the first section, description of functional verification, verification methodology, regression tests and evolutionary algorithms is provided. In the following section, the evolutionary algorithm, the purpose of which is to achieve reduction of the number of test vectors obtained in the process of functional verification, is proposed. Afterwards, the proposed algorithm is implemented and a set of experiments is evaluated. The results are discussed.
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SystemVerilog Framework for DMA Controllers Verification
Zachariášová, Marcela ; Martínek, Tomáš (referee) ; Puš, Viktor (advisor)
In contemporary hardware design, verification techniques are exploited to verify the function of hardware components as well as complex systems. This thesis deals with functional verification of DMA controllers. It describes the theoretical principles of verification using the SystemVerilog language and the principles of DMA data transfer. The design of controllers is described, with the focus on design of the verification environment and results of the verification.
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Diagnostics Research Group Information System
Vaďura, Pavel ; Zachariášová, Marcela (referee) ; Čekan, Ondřej (advisor)
This thesis discusses the design and implementation of an information system for a research group. The basic technologies for the creation of an information system such as PHP, PHP frameworks, MySQL and jQuery are described. Another part deals with the specification, analysis, design and implementation reflecting the requirements of the research group on the functionality of the information system.
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Functional Verification of Robotic System Using UVM
Krajčír, Stanislav ; Čekan, Ondřej (referee) ; Zachariášová, Marcela (advisor)
One of the currently most used approaches for verification of hardware systems is functional verification. This master thesis describes design and implementation of a verification environment using UVM (Universal Verification Methodology) methodology for verifying the correctness of the robot controller in order to eliminate functional errors and faults of its implementation. The theoretical part of the thesis describes the basic information about functional verification, methodologies for creating verification environments, the SystemVerilog language and fault tolerance methodologies. The next part of thesis focuses on the design of the verification environment, its implementation and the creation of tests used to verify the correctness of the robot controller. Results of verification are discussed and evaluated in the conclusion of this work.
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