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Design of sigma-delta digital-to-analog converter in CMOS technology
Soukup, Luděk ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This master’s thesis deals with the issue of digital to analog conversion and possibility of its realization in digital circuits. Goal of this project is to design sigma-delta digital to analog converter with resolution of 14 bits and frequency band (0 ÷ 20) kHz. Main functional blocks: interpolator and modulator sigma-delta will be realized like digital structures. Reconstruction filter will be realized like an analog structure. For design a check of parameters of designed converter programs MATLAB and Simulink are used. Designed digital structures will be described by VHDL language.
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Measurement parameters of communication via PCI Express
Dujiček, Ondřej ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This bachelor thesis deals with parameters affecting throughput of PCI Express bus and its main result is a design and implementation of a unit for measuring parameters of communication over PCI Express bus. The unit is implemented in VHDL language and its support on generating and measuring traffic at speeds up to 100 Gbps. Unit’s operation frequency, when implemented in Virtex 7 available at COMBO-100G , is 200 MHz. The implemented unit is controlled from software through MI32 interface and it is able to measure the amount of transferred packets and data in both receive and transmit directions. This information can be exported into software using MI32 interface.
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Design of selected IEEE 802.1Q standard parts
Kliment, Filip ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This thesis deals with network substandards from the TSN group (IEEE 802.1Q), which deal with prioritization of network traffic in TSN networks. These sub-standards include 802.1QBV and 802.1QBU, which have been described in more detail and compared in terms of network permeability and latency. Substandard 802.1QBU was chosen for the design implementation in FPGA. The design was described in VHDL. The devloped design was verified by simulations, using self-tests. The work includes synthesis and time analysis.
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Implementation of 400 Gb/s Ethernet PCS layer to FPGA
Kolařík, Jaroslav ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This master thesis deals with the design of the 400GBASE-R PCS in accordance with the IEEE 802.3bs-2017 standard which defines 400 Gbps Ethernet. The first part of this thesis focuses on general architecture of FPGA and its possible variants for implementation for 400 Gbps Ethernet communication, therefore there is description of those architectures and its resources. The next part describes progression of the Ethernet and its connection to the ISO/OSI reference model. The next section of this thesis is about description of physical layer of Ethernet for 400 Gbps version, after which follows design of PCS unit and its implementation with use of resources of selected FPGA. In the last part of this thesis is description of the simulation of the implemented unit. Achieved results and outcomes of this master thesis are evaluated in a conclusion.
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Audio synthesizer in FPGA chip
Tomko, Jakub ; Pristach, Marián (referee) ; Bohrn, Marek (advisor)
This thesis analyses methods of sound synthesis. Advantages and disadvantages of application of individual methods in music synthetizers are evaluated. Based on piano sound analysis, the suitable method for synthesizer's design is chosen. Synthesizer has been implemented in FPGA of Spartan-3 Development Board.
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Graphical user interface for filter design
Tesařík, Jan ; Kledrowetz, Vilém (referee) ; Pristach, Marián (advisor)
This work deals with design of program that allows to generate VHDL description from connection of filters. Its main aim is to create graphical extension on existing program and connect it to VHDL generator. Output from program will be XML file of created connection and generated VHDL description. Design of program was done by using Qt Framework environment and C++ language.
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Customizable rear combination lamp module with HD resolution
Prokš, Jiří ; Pristach, Marián (referee) ; Kledrowetz, Vilém (advisor)
This thesis deals with the design of LED matrix array contains 150 LEDs. In the first part, the thesis identifies source of light like OLED and LED and provide an overview of their lifetime, reliability and basic principle of design systems with LEDs. The thesis then describe design of LED matrix array, deals with power supply of this LED array and with cooling of LED. Finally the thesis describes a software for contol of LED matrix array.
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Graphics controller for FPGA
Rolko, Maroš ; Bohrn, Marek (referee) ; Pristach, Marián (advisor)
This diploma thesis is about design of a 2D graphics controller for FPGA circuits. It consists of two parts. In the first phase, it analyses 2D acceleration and interface for communication with display devices of the operation system Linux. The second part contains design of graphics controller itself and its implementation. Part of the thesis is description of components that the controller consists of and evaluation of resultant implementation. For testing purposes on selected FPGA circuit, test modules adding support for used peripherals and test data generation are created.
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Device for recording data on memory card
Čaloun, Petr ; Šteffan, Pavel (referee) ; Pristach, Marián (advisor)
This work deals with design of devices for recording data using programmable gate array. The paper describes the principle of communication protocols used for communication with a memory card. The next part describes the selection of different interfaces, communication protocols and describes the design of data storage devices. The last part is focused on design of application for long time data collection.
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