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Statefull Processing of TCP/IP Flows
Košek, Martin ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
Network security systems become an essential part of many network structures in both company and university domains. These systems however require a~higher semantic level of network traffic analysis like statefull filtration or TCP stream reassembling. This bachelor work deals with an architecture of flexible network platform capable of statefull processing at multigigabit speeds. It allows to analyze and process incoming network traffic with a flow-based approach rather than packet-based one. The proposed architecture is flexible in supporting wide range of applications, allows performance scalability and state information consistency checking. The advantages and flexibility of proposed platform is demonstrated on several network security applications.
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High-Frequency Trading Using External DRAM
Nevrkla, Lukáš ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The primary part of low-latency trading is a machine that can trade with lower latency than any other trader. Hardware-accelerated platforms can reduce trading latency down to hundreds of nanoseconds. This work focuses on a specific data structure (Order Book) inside this hardware platform that manages the current market price levels. The current implementation manages this data structure inside the software of the hosting machine, and only a few best price levels are inside the hardware. Synchronization between hardware and software has a latency in the order of microseconds. Therefore the best price levels are sometimes unavailable inside the hardware platform. This work presents a solution for managing this structure inside FPGA while saving its content inside the external dynamic memory. The new solution reduces the latency down to 150–200 nanoseconds with occasional (2 % cases) increase to 450–650 nanoseconds. Lower latency will help the trading platform react faster to larger stock market changes which are very important for traders.
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Testing of Probes for Network Traffic Monitoring
Sobol, Jan ; Korček, Pavol (referee) ; Kořenek, Jan (advisor)
In order to ensure a secure and stable Internet, administrators need tools for network monitoring which will allow them to analyze ongoing network traffic and respond to situations in a timely manner. One way to monitor traffic is to use monitoring probes. This thesis focuses on a thorough verification of the parameters of existing probes IPFIX probe and FlexProbe. FlexProbe is a network probe designed for the implementation of lawful interceptions developed at FIT BUT in cooperation with the Police of the Czech Republic. The IPFIX probe is developed by the CESNET association and is used for flow monitoring within the FlexProbe probe. In order to be able to operate the probes in the target environment for a long time, it is necessary to thoroughly test the device. The exact behavior of the probe is defined by the specification requirements that are developed for both probes. Based on the requirements, a comprehensive test system covering functional and performance parameters of the probes was designed. The tests are unified using a test framework and included in automated scenarios implemented in system Jenkins. At the end of the thesis, the coverage of the required properties of the probes and their performance is evaluated.
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Hardware Acceleration Demo on the Pynq Z2 Board
Vosyka, Pavel ; Kekely, Lukáš (referee) ; Kořenek, Jan (advisor)
The work deals with a hardware acceleration on the Zynq platform with Pynq technology. Three examples demonstrating hardware acceleration were designed for teaching purposes. The effort was to make examples as simple as possible to make them easy to understand. Hardware accelerators are implemented in VHDL language and driven by implemented Python application. The examples were successfully implemented and evaluated.
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Hardware Acceleration of Encryption Algorithms Using Xilinx Zynq Technology
Linner, Marek ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The main concern of this paper are two world standard encryption algorithms Data Encryption Standard DES (DES for short) and Advanced Encryption Standard (further mentioned as AES). For these two respective algorithms, three publicly available implementations are integrated into a benchmarking code in C programming language. The code has been executed, implementations measured with three different input block lengths and bitrate calculated for each implementation. The thesis also includes hardware implementation of both encryption algorithms DES and AES using VHDL language, simulation of the synthesised circuits and calculation of the hardware implementations' bitrate using Vivado simulator's timing reports. These measured bitrates are then compared with the bitrates of benchmarked software implementations. Paper includes all source codes of the benchmarking C program and VHDL implementation, along with program written in C# used to generate VHDL components and another C# program used for automated testing.
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Implementation of Encryption Algorithms in VHDL Language
Fruněk, Lukáš ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The thesis deals with the design and implementation of the encryption algorithms DES and AES, operating in the CTR mode. The designed modules are implemented in the VHDL language and are mapped in the FPGA Intel Arria 10 SX 480. Algorithms are optimized for maximum throughput using loop unrolling and inner pipelining. The encryption module for DES reaches throughput of 26.2 Gbit/s with the circuit operating 410 MHz, and the module for AES reaches throughput of 34.6 Gbit/s with the circuit operating at 271 MHz. The reached throughput is in the order of thousand times faster than of the same encryption algorithms implemented in software for built-in microprocessors.
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Anomaly Detection in IoT Networks
Halaj, Jozef ; Hujňák, Ondřej (referee) ; Kořenek, Jan (advisor)
The goal of the thesis was an analysis of IoT communication protocols, their vulnerabilities and the creation of a suitable anomaly detector. It must be possible to run the detector on routers with the OpenWRT system. To create the final solution, it was necessary to analyze the communication protocols BLE and Z-Wave with a focus on their security and vulnerabilities. Furthermore, it was necessary to analyze the possibilities of anomaly detection, design and implement the detection system. The result is a modular detection system based on the NEMEA framework. The detection system is able to detect re-pairing of BLE devices representing a potential pairing attack. The system allows interception of Z-Wave communication using SDR, detection of Z-Wave network scanning and several attacks on network routing. The system extends the existing detector over IoT statistical data with more detailed statistics with a broader view of the network. The original solution had only Z-Wave statistics with a limited view of the network obtained from the Z-Wave controller. The modular solution of the system provides deployment flexibility and easy system scalability. The functionality of the solution was verified by experiments and a set of automated tests. The system was also successfully tested on a router with OpenWRT and in the real world enviroment. The results of the thesis were used within the SIoT project.
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Integration of New Wireless Technologies and Devices into the BeeeOn Gateway
Bednařík, David ; Korček, Pavol (referee) ; Kořenek, Jan (advisor)
This master thesis deals with the integration of new devices from the manufacturers Revogi, Tabu Lumen, Sonoff and HomeMatic into the BeeeOn Gateway software. The theoretical part deals with the architecture of the BeeeOn Gateway software and describes the characteristics, behavior and way of communication with devices from the above mentioned manufacturers. This part of thesis also contains a description of the communication technologies used by these devices. They include Bluetooth Low Energy, the WiFi and the 868 MHz radio. The practical part mentions the way of extension of BeeeOn Gateway software to modules that implement support for smart devices. This section also describes how the correctness of implementation was verified and testing of the entire BeeeOn Gateway software. The testing of gateway is performed by unit and integration tests, which verify the behavior of individual gateway components as well as the whole gateway.
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Processing Unit for Analysis and Modification of Network Traffic
Pazdera, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This paper deals with the design and implementation of the Processing Unit for Analysis and Modification of Network Traffic. The proposed unit is intended to analyse an incoming network traffic and perform packet header editations to provide the proper packet delivery. The designed architecture has the following characteristics. It is based on the stream processor concept which allows to process independent stream elements (i.e. packets) in parallel. Multiply stream clients can be used to process the same stream data concurrently. The stream clients can be driven either autonomously or by program. The packets are processed according to the incoming metadata and transmited to the output. The Processing Unit has been implemented in VHDL language. The target technology is Field Programmable Gate Array (FPGA).
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Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
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