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Verification of digital circuit Microcore GNSS Baseband
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the master´s thesis is to verify Acquisition Engine and Tracking Engine in the Microcore GNSS Baseband digital circuit from Honeywell. Theoretical part contains a brief introduction into the satellite position determination, basic principles of the verified blocks is given and UVM methodology is introduced. Practical part contains requirements, test cases and test procedures. The verification environment is also described. In the last part of the thesis is the verification process and it´s results.
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Data aquisition card for integrated circuit tester
Koleček, Jan ; Pristach, Marián (referee) ; Dvořák, Vojtěch (advisor)
The goal of this bachelor's thesis is to design and realize a data acquisition card. The main task of the designed card will be to generate stimulating signals for the tested integrated circuit, to process signals generated by the tested integrated circuit, to convert them into a digital form and to send them to a superior system. The thesis will present a choice of integrated circuits suitable for its realization, a wiring diagram of the data acquisition card, PCB design and VHDL code for the control FPGA chip.
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AVR microprocessor implementation on FPGA
Hájek, Radek ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This bachelor‘s thesis deals with FPGA implementation of Atmel AVR core described using VHDL language. Basic architecture concepts and processor addressing modes are summarized in this thesis. The core including several peripherals was designed to be compatible with ATtiny26 architecture and instruction set. The microprocessor was described in VHDL and verified in several types of tests.
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Semi-automated Design of High-performance Digital Circuits with Xilinx FPGAs
Houška, David ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
Tato diplomová práce se zabývá návrhem sekvenčních digitálních obvodů s ohledem na optimalizaci zpoždění. V práci je popsána problematika dvou technik, které jsou běžně používané při optimalizaci – stručně je popsána technika tzv. synchronizace registrů (angl. retiming), větší pozornost je však věnována technice tzv. zřetězení (angl. pipelining). V rámci praktické části byla vypracována forma abstrakce sekvenčních digitálních obvodů pomocí acyklických orientovaných grafů. Obvod je tak přenesen do roviny, ve které je jednodušší jej transformovat. Zároveň je představen nástroj pro polo-automatickou optimalizaci digitálních obvodů vyvíjených v prostředí Xilinx ISE Design Suite využitím techniky zřetězení.
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SpaceWire Endpoint verification
Peroutka, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of the bachelor´s thesis is the verification of the SpaceWire endpoint IP core created at Department of Microelectronics, Faculty of Electrical Engineering and Communication, VUT Brno. The thesis has 3 major parts. The first part briefly describes the SpaceWire standard. The second part deals with the theoretical description of the verification. The last part deals with the verification of the SpaceWire endpoint.
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Data protection in SRAM type memory with error correction code
Záhora, Jakub ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The thesis contains basic concepts necessary for understanding the theory of coding. It then explains the parameters that will be monitored for the described codes. Based on the criteria, it selects the BCH code and the Extended Hamming Code, as appropriate, and further compares their properties to select a more efficient code from this pair. As a result of the comparison, it selects the Extended Hamming Code as more suitable for the subsequent design of the program. The code design procedures, tests that verify the functionality of the code, and the resources used for the Spartan-3 circuit to implement the code for the Spartan-3 circuit are then shown.
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Implementation of 8-bit microprocessor into FPGA chip
Walletzký, Ondřej ; Dvořák, Vojtěch (referee) ; Bohrn, Marek (advisor)
This thesis deals with design of microprocessor compatible with one of 8-bit microcontrollers manufactured by Microchip company. Theoretical part of this thesis analyzes architectures of 8-bit PIC microcontrollers, picks one of these microcontrollers and describes its architecture and function of its subcircuits. Practical part deals with design of architecture compatible in terms of instruction execution, internal data flow and subcircuit behavior, all this to achieve the best possible program portability from target microcontroller. The last part of thesis describes method of processor implementation into FPGA chip and mentions potential design differences for ASIC implementation. It also deals with verification and method of programming.
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Modelling and simulation of analog circuits in FPGA
Kotulič, Dominik ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
Bachelor thesis is focused on seeking a suitable calculation algorithm of an exponential function which could be suitably implemented in ASIC and FPGA circuits. The first part of the thesis is aimed at brief clarifying of the issue of transients in accumulation circuits and their modelling in the program PSpice. The second part deals with seeking ways of model proposals of the exponential function appropriate for the implementation in ASIC and FPGA circuits. Subsequently, in the final part of the thesis we designed and tested two calculation algorithms of the model of the exponential function that are implemented for floating point numbers.
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Network traffic processing at very high speed
Cabal, Jakub ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Different network devices require processing of the network traffic. To process the network traffic, it is necessary to parse headers of particular protocols packed in incoming ethernet frames. The processed headers can be repackaged to ethernet frames and sent back to the network. The goal of this thesis is to design and implement a circuit for analysis and parsing of ethernet frames, together with circuit for deparsing ethernet frames. The circuits are designed for throughputs of up to 400 Gb/s. The circuits are implemented for the FPGA technology.
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