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Packet Transmission at 100 Gb/s Ethernet
Hummel, Václav ; Dvořák, Milan (referee) ; Matoušek, Jiří (advisor)
The NetCOPE platform is used for rapid developement of hardware accelerated network applications on the family of COMBO cards. An essential part of this platform is output network module which helps designers to implement Data Link Layer of the OSI reference model, especially the MAC sublayer. This bachelor’s thesis focuses on design, implemen- tation and verification of such a module operating at speed 100 Gb/s. Furthemore, an appli- cation on the NetCOPE platform was created. It is designed for transmitting short samples of network traffic stored in QDR static memory. Transmission is controlled by precise ti- mestamps. The whole system was deployed on a COMBO card and verified by a network traffic analyzer.
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Distribution of Network Traffic to Multi-Core Processors
Straňák, Peter ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The content of this thesis is the design and implementation description of the driver for the NetCOPE platform. This driver is required to provide rapid transfer between hardware and software as well as multi-threaded applications. Driver is designed for Linux and is modified so that it allows multiple applications simultaneous access to the card. The paper provides basic information necessary for its adaptation and implementation details of individual features. The emphasis is on high data throughput. The part of the implementation is also a modification of the user library, which cooperates with the driver.
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Graphical User Interface for Packet Generator
Chromčák, Michal ; Kováčik, Michal (referee) ; Matoušek, Jiří (advisor)
According to increasing requirements on speed of different software and hardware components, there are solutions, which can, by principle, reach better parameters, then solutions commonly known. One of them is to use software with hardware acceleration on the field of generating synthetic network traffic. Exactly this way a packet generator was implemented, in current version without graphical user interface. But to let this system spread into the target group of users, there is need to implement also this interface. This bachelor's thesis describes proposal of graphical interface, its implementation in JavaFX programming language, testing on real users and tutorial demonstrating how to use this interface.
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Implementation and Verification of Network Interface Blocks
Matoušek, Jiří ; Kaštil, Jan (referee) ; Tobola, Jiří (advisor)
Network interface blocks are basic part of the NetCOPE platform where they help to the network application designers to deal with problems of implementing the Data Link Layer of the OSI Reference Model, especially the MAC sublayer. This thesis is focused on the design and implementation of such network interface blocks operating at speed 10 Gb/s. Designed input interface block provides checking of several parts of the Ethernet frame and allows discarding of this frame based on checking results. Output interface block supports replacing frame's Source Address by a pre-set value and provides frame's CRC computation. Both network interface blocks also include a set of frames counters. Implemented network interface blocks were tested on the COMBO card. SystemVerilog verification testbench was also designed for both network interface blocks.
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Design of Network Applications for a NetCOPE Platform
Hank, Andrej ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
Monitoring and security in multigigabit networks with speeds 1 - 100 Gb/s needs hardware acceleration. NetCOPE platform for rapid development of network applications uses hardware acceleration card with FPGA technology by means of hardware/software codesign. Increas in performance of platform's software part is dependent of parallel processing in applications to take advantage of utilising more processor cores. This thesis analyses NetCOPE platform architecture and possibilities of parallelising classic network applications and creates models of concurrent access to data in NetCOPE platform to utilize more processor cores. These models are subsequently implemented as extensions to platform's Linux system drivers. Userspace libraries are created to provide simple interface for applications to use these new features. To achieve high throughput of this solution several optimizations are performed. Results are measured by created testing tools.
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Hardware Packet Preprocessing for Acceleration of Network Applications
Vondruška, Lukáš ; Mikušek, Petr (referee) ; Tobola, Jiří (advisor)
This thesis particularly deals with design and implementation of FPGA unit, which performs hardware acclerated header field extraction of network packets. By utilizing NetCOPE platform it is proposed flexible and effective high-peformance solution for high-speed networks. A theoretical part presents a classical protocol model and an analysis of the Internet traffic. Main part of the thesis is further focused on key issues in hardware packet preprocessing, such as packet classification and deep packet inspection. The author of this thesis also discusses possible technology platforms, which can be utilized to acceleration of network applications.
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Stateful Firewall for FPGA
Žižka, Martin ; Kajan, Michal (referee) ; Puš, Viktor (advisor)
This thesis describes the requirements analysis, design and implementation of stateful packet filtering to an existing stateless firewall. They also deals with testing of the implemented system. The first two chapters describe the properties NetCOPE development platform for FPGA. They also describes the principle of operation firewall, which also serves as a requirements specification for stateful firewall. Then describes the detailed design of individual modules to modify the existing firewall and the proposal for the creation of new modules. It also discusses the implementation of the proposed modules and testing for proper operation. Finally, it discuss the current state of the thesis and describes possible future expansion.
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Protection of highspeed communication systems
Smékal, David ; Martinásek, Zdeněk (referee) ; Hajný, Jan (advisor)
The diploma thesis deals with 128–bit AES data encryption and its implementation in FPGA network card using VHDL programming language. The theoretical part explains AES encryption and decryption, its individual steps and operating modes. Further was described the VHDL programming language, development environment Vivado, FPGA network card Combo–80G and configurable framework NetCOPE. The practical part is the implementation of AES–128 in VHDL. A simulation was used to eliminate errors, then the synthesis was performed. These steps were made using Vivado software. Last step of practical part was testing of synthesized firmware on COMBO–80G card. Total of 4 projects were implemented in FPGA card. Two of them were AES encryption and decryption with ECB mode and another two describe the encryption and decryption with CBC mode.
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Routing in High-speed Computer Networks
Vlček, Lukáš ; Hanák, Pavel (referee) ; Škorpil, Vladislav (advisor)
Goal of this master thesis is to introduce and bring up basics and principles of NetCOPE framework in many details using "first approach" method for exploration of its internal structures - mainly focusing on application core using VHDL for focus itself. Furthermore, this knowledge is used for design and implementation of filtration system for network traffic with more details within phase of design in VHDL language.
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