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Picture generation using path tracing
Áč, Ondřej ; Dvořák, Vojtěch (referee) ; Pavlík, Michal (advisor)
This thesis deals with the problematics of computer-generated imagery using path tracing. The goal of this work is to create interactive computer program, which allows editing and rendering of photorealistic images of various scenes in real time. The work presents the concept of rendering equation, along with its known solutions, in the theoretical part of the work. Thesis describes in detail the solution using path tracing, based on the Monte Carlo integration technique, along with the benefits, it provides compared to the other techniques. Several hardware and software optimizations are then presented. Practical part of the work focuses on analysis of C++ source code and compiled assembly code whilst using hardware specific SIMD optimizations. Mandatory part of work is also the demonstration of program’s functionality, along with the measurements of achieved performance gains using manual optimizations.
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SIMD code generator
Tuček, Karel ; Bednárek, David (advisor) ; Arcaini, Paolo (referee)
Title: SIMD code generator Author: Karel Tuček Department: Department of Software Engineering Supervisor: RNDr. David Bednárek, Ph.D., Department of Software Engineering Abstract: The center of our interest is a problem of pipelined realisation of a special case of data processing networks. These realisations are supposed to realise some computations on series of independent data sets while utilizing SIMD instructions. The aim of this paper is to theoretically investigate the possibilities and the problems of employment of control flow in these networks and also to implement a general framework suitable for generation of these realisations. The main idea is utilisation of an algorithm crawling over partitions of a network factorised with respect to its control flow. Our idea is that SIMD parallelism should take place on the same instruction realised across multiple data sets. We illustrate the problems relevant to employment of branching and loops in these networks. We especially discuss a problem of data ordering and also provide relevant proofs. In the analytical part, we show implementation of a general framework which we believe to be suitable for processing of these networks. We also provide examples utilising Intel's SIMD Streaming Extensions. Keywords: Processing networks SIMD Parallelism iii
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Algortihm Optimization Using SIMD Instructions
Sedláček, Marek ; Rydlo, Štěpán (referee) ; Orság, Filip (advisor)
This thesis talks about techniques which can be used to optimize run time of algorithms. For a demonstration of these techniques algorithms from different fields were chosen, namely particle swarm optimization, circle drawing algorithm and image (matrix) rotation algorithm. These algorithms were written in Python 3, C language and assembly language using SIMD instructions. While writing these codes emphases was placed on code efficiency. These practices were in this thesis described and compared, same as the impact on algorithm optimization. Performed tests upheld expected potential of SIMD technology for optimization, but also that this approach cannot be used in all cases. In case of circle drawing the SIMD approach achieved more than ten times better speeds than the serial implementation in C and more than one thousand times better speed than Python 3 implementation. In case of particle swarm optimization the result was opposite -- serial C implementation achieved a better speed than SIMD implementation.
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.NET's LINQ Optimization
Šerý, Daniel ; Ryšavý, Ondřej (referee) ; Pluskal, Jan (advisor)
This thesis deals with LINQ (Language integrated query) and investigates possibilities of its implementation and optimization in C# language. Method of rewriting of query to procedural code is chosen and implemented. The goal is to provide a LINQ that can be used in code with the need for high speed. Regarding the program created for rewriting LINQ queries, the performance of most operators has been increased by 1.2x to 20x of System.Linq speed depending of rewritten algorithm, data source and provided information to rewriting program.
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SIMD code generator
Tuček, Karel ; Bednárek, David (advisor) ; Arcaini, Paolo (referee)
Title: SIMD code generator Author: Karel Tuček Department: Department of Software Engineering Supervisor: RNDr. David Bednárek, Ph.D., Department of Software Engineering Abstract: The center of our interest is a problem of pipelined realisation of a special case of data processing networks. These realisations are supposed to realise some computations on series of independent data sets while utilizing SIMD instructions. The aim of this paper is to theoretically investigate the possibilities and the problems of employment of control flow in these networks and also to implement a general framework suitable for generation of these realisations. The main idea is utilisation of an algorithm crawling over partitions of a network factorised with respect to its control flow. Our idea is that SIMD parallelism should take place on the same instruction realised across multiple data sets. We illustrate the problems relevant to employment of branching and loops in these networks. We especially discuss a problem of data ordering and also provide relevant proofs. In the analytical part, we show implementation of a general framework which we believe to be suitable for processing of these networks. We also provide examples utilising Intel's SIMD Streaming Extensions. Keywords: Processing networks SIMD Parallelism iii
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Acceleration of Vector and Cryptographic Operations on x86-64 Platform
Šlenker, Samuel ; Martinásek, Zdeněk (referee) ; Balík, Miroslav (advisor)
The aim of this thesis was to study and subsequently process a comparison of older and newer SIMD processing units of modern microprocessors on the x86-64 platform. The thesis provides an overview of the fastest computations of vector operations with matrices and vectors, including corresponding source codes. Furthermore, the thesis is focused on authenticated encryption, specifically on block cipher AES operating in Galois Counter Mode, and on a discussion of possibilities of instruction sets for cryptographic support.
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Acceleration of Object Detection Using Classifiers
Juránek, Roman ; Kälviäinen, Heikki (referee) ; Sojka, Eduard (referee) ; Zemčík, Pavel (advisor)
Detekce objektů v počítačovém vidění je složítá úloha. Velmi populární a rozšířená metoda pro detekci je využití statistických klasifikátorů a skenovacích oken. Pro učení kalsifikátorů se často používá algoritmus AdaBoost (nebo jeho modifikace), protože dosahuje vysoké úspěšnosti detekce, nízkého počtu chybných detekcí a je vhodný pro detekci v reálném čase. Implementaci detekce objektů je možné provést různými způsoby a lze využít vlastnosti konkrétní architektury, pro urychlení detekce. Pro akceleraci je možné využít grafické procesory, vícejádrové architektury, SIMD instrukce, nebo programovatelný hardware. Tato práce představuje metodu optimalizace, která vylepšuje výkon detekce objektů s ohledem na cenovou funkci zadanou uživatelem. Metoda rozděluje předem natrénovaný klasifikátor do několika různých implementací, tak aby celková cena klasifikace byla minimalizována. Metoda je verifikována na základním experimentu, kdy je klasifikátor rozdělen do předzpracovací jednotku v FPGA a do jednotky ve standardním PC.
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Lifting Scheme Cores for Wavelet Transform
Bařina, David ; Kälviäinen, Heikki (referee) ; Sojka, Eduard (referee) ; Zemčík, Pavel (advisor)
Práce se zaměřuje na efektivní výpočet dvourozměrné diskrétní vlnkové transformace. Současné metody jsou v práci rozšířeny v několika směrech a to tak, aby spočetly tuto transformaci v jediném průchodu, a to případně víceúrovňově, použitím kompaktního jádra. Tohle jádro dále může být vhodně přeorganizováno za účelem minimalizace užití některých prostředků. Představený přístup krásně zapadá do běžně používaných rozšíření SIMD, využívá hierarchii cache pamětí moderních procesorů a je vhodný k paralelnímu výpočtu. Prezentovaný přístup je nakonec začleněn do kompresního řetězce formátu JPEG 2000, ve kterém se ukázal být zásadně rychlejší než široce používané implementace.
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Compilation of OpenCL Applications for Embedded Systems
Šnobl, Pavel ; Čekan, Ondřej (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the support for compilation and execution of programs written using OpenCL framework on embedded systems. OpenCL is a system for programming heterogeneous systems comprising processors, graphic accelerators and other computing devices. But it also finds usage on systems composed of just one computing unit, where it allows to write parallel programs (task and data parallelism) and work with hierarchical system of memories. In this thesis, various available open source OpenCL implementations are compared and one selected is then integrated into LLVM compiler infrastructure. This compiler is generated as a part of toolchain provided by application specific instruction set architecture processor developement environment called Codasip Studio. Designed and implemented are also optimizations for architectures with SIMD instructions and VLIW architectures. The result is tested and demonstrated on a set of testing applications.
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