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Processor Model Creation Using ADL Language
Ostatník, Kristián ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The goal of this thesis is to create an instruction-accurate model of ARC processor using the CodAL ADL language. The first part is dedicated to classification of processors and ADL languages. The second part describes the implementation process and the generation of C/C++ compiler for debugging and verification of the created model. At the end the created model is compared to an existing model ARC 700 on a set of benchmark tests.
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SystemC Memory Subsystem
Michl, Kamil ; Vaňák, Tomáš (referee) ; Hruška, Tomáš (advisor)
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
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Architecture Information for LLVM Compiler Optimizations
Svoboda, Jan ; Dolíhal, Luděk (referee) ; Hruška, Tomáš (advisor)
Tato práce se zabývá automatickou extrakcí informací o architektuře procesoru z jazyka CodAL. Získané informace jsou využity jako základ pro cenový model optimalizátoru překladače LLVM. V rámci práce vznikl nový systém, který vytváří cenový model, převádí jej do C++ kódu a sestavuje do dynamické knihovny. Tato knihovna je za běhu načtena překladačem a využita pro přesnější rozhodování o přínosech jednotlivých optimalizací. Výsledkem práce je průměrné 14% snížení velikosti strojového kódu programů a až 68% zlepšení výkonu generovaného kódu.
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C Compiler for VLIW Architectures
Mináč, Tomáš ; Husár, Adam (referee) ; Masařík, Karel (advisor)
This work discusses about CodAl language and Codasip framework. It describes LLVM compiling platform, LLVM IR and its possible optimizations. The result of this work is creation and implementation a proposal of global scheduling dependence on profile as extension in LLVM.
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Software Pipelining in the LLVM Compiler
Glasnák, Ondrej ; Hynek, Jiří (referee) ; Masařík, Karel (advisor)
This thesis discusses a design and implementation of the Software Pipelining, a optimization technique of loops in a program, which tries to exploit instruction-level parallelism. It is achieved by scheduling instructions in a way to overlap iterations of the loop and therefore execute them in a pipeline. This way optimization speeds up the final program. There is a detailed description of design and implementation of Swing Modulo Scheduling algorithm, an effective and efficient method for finding near-optimal plans for software-pipelined loops. This work has been done as a part of a larger project, the development of Codasip Framework. Part of this framework is the retargetable C compiler based on compiler architecture LLVM, in which this work is implemented.
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Modelling of PowerPC Processor
Blaha, Hynek ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Processor architectures are becoming increasingly complex, so great emphasis is put on the automation of their desings. This bachelor thesis describes the design of the PowerPC processor architecture in Codal language. The model is created according to avaliable documentation. The functionality and efficiency of the model was verified by tests provided by research group Lissom and compared to current competitor.
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Debugging Information in Linker
Nikl, Vojtěch ; Křoustek, Jakub (referee) ; Masařík, Karel (advisor)
This thesis describes the conversion between the CCOFF object file format and the ELF file format. We start with a general object file format and its debbuging information, then we focus closely on the ELF, CCOFF and DWARF debugging information. The functionality of the CCOFF format is encapsulated in the ObjectFile class library. Then follows the description of creating an ELF object file, its filling with the proper data and its conversion back to the CCOFF format.
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Compilation of C++ Applications for Embedded Devices
Nosterský, Milan ; Přikryl, Zdeněk (referee) ; Hruška, Tomáš (advisor)
This master's thesis deals with the integrations of C++ programming language and its standard C++11 into the compiler for embedded systems. This compiler is based on LLVM project and it is generated from Codasip Studio. Codasip Studio is tool for design of the aplication specific processor cores, it is also allows generate compiler, which is based on the description of semantics section in processor's instruction set for any target processor architecture. C++ is programming language based on the C, which is extended by object oriented design and many other features. C++ language allows writing of very effective code on high level of abstraction. Funcionality of implementation is tested on testsuite in last phase of master's thesis.
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Specialized Instruction Design
Koscielniak, Jan ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The purpose of this thesis is to design and implement specialized instructions for RISC-V instruction set architecture. These instruction are used to accelerate a set of selected cryptographic algorithms. New instructions are implemented in Codasip Studio for 32bit processor model with RV32IM instruction set. Open source implementations were selected and edited to use new instructions. Instructions were used on respective algorithms, tested and profiled. The outcome of this thesis is instruction set extension, that enables up to seven times speed up, depending on used algorithm.
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Processor Model Creation Using ADL Language
Ostatník, Kristián ; Zachariášová, Marcela (referee) ; Hruška, Tomáš (advisor)
The goal of this thesis is to create an instruction-accurate model of ARC processor using the CodAL ADL language. The first part is dedicated to classification of processors and ADL languages. The second part describes the implementation process and the generation of C/C++ compiler for debugging and verification of the created model. At the end the created model is compared to an existing model ARC 700 on a set of benchmark tests.
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