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Implementation of modular arithmetic in FPGAs and ASICs
Sýkora, Michal ; Bohrn, Marek (referee) ; Dvořák, Vojtěch (advisor)
This thesis is focused on analysis, design and implementation of modular arithmetic in FPGAs and ASICs. Its main objective is to create a C++/SystemC library, that contains synthesizable functions for operations with Montgomery reduction in modular arithmetic. Results of the implementation of Montgomery reduction are compared with results of classic algorithms for modular arithmetic.
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Modelling and simulation of analog circuits in FPGA
Kotulič, Dominik ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
Bachelor thesis is focused on seeking a suitable calculation algorithm of an exponential function which could be suitably implemented in ASIC and FPGA circuits. The first part of the thesis is aimed at brief clarifying of the issue of transients in accumulation circuits and their modelling in the program PSpice. The second part deals with seeking ways of model proposals of the exponential function appropriate for the implementation in ASIC and FPGA circuits. Subsequently, in the final part of the thesis we designed and tested two calculation algorithms of the model of the exponential function that are implemented for floating point numbers.
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Design of hardware cipher module
Bayer, Tomáš ; Stančík, Peter (referee) ; Sobotka, Jiří (advisor)
This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.
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