|
|
Mapping of Algorithms to FPGA Using High-Level Synthesis Tools
Kupka, David ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis deals with ways to describe hardware. It presents the methods used in the synthesis of the description and then it compares on a set of algorithms currently common low level description in VHDL with the newly emerging high-level synthesis, where a component is described at a algorithmic level in higher programming language. The object of comparison is the ratio of time required for implementation and optimality of the resulting components.
|
|
|
P4.16 Compiler Using High Level Synthesis
Neruda, Jakub ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
The P4 language is currently a hot topic in the field of network administration due to its capability to program the functionality of network devices. This language is still in development and its last revision P416 drastically changed not only the language features and syntax, but also the underlying compiler. The CESNET association supports the development of the P4 language and thus they also need to support the new standard. This work examines possible problems tied to migration, namely issues related to translation of high-level user-defined actions into VHDL description, with the help of High-level Synthesis (HLS), instantiation of so-called extern objects and the support of atomic sections. The text discusses possible ways of interconnecting the HDL components and organisation of their memory space in order to support configuration from software at runtime. The architecture of the p4c compiler is also described, complete with code examples implementing core classes participating in the compilation process. The last part of the work showcases the usage of Vivado HLS for optimizing C++ code in order to get maximum performance from the resulting firmware.
|
|
|
HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
|
|
|
High level synthesis in network applications described using P4 language
Panák, Petr ; Šťáva, Martin (referee) ; Fujcik, Lukáš (advisor)
High-level synthesis is a compelling method of designing a digital circuit. High abstraction and faster verification are advantages which aren't pressent in Register Transfer Level designing. That guarantees faster designing with lower development costs. This bachelor thesis deals with a digital design of actions, extern blocks and MI32 interface access. Each component design is described using C/C++ programming language and synthesised with Intel HLS compiler.
|
|
| |
|
|
Implementation of matrix decomposition and pseudoinversion on FPGA
Röszler, Pavel ; Rajmic, Pavel (referee) ; Smékal, David (advisor)
The purpose of this thesis is to implement algorithms of matrix eigendecomposition and pseudoinverse computation on a Field Programmable Gate Array (FPGA) platform. Firstly, there are described matrix decomposition methods that are broadly used in mentioned algorithms. Next section is focused on the basic theory and methods of computation eigenvalues and eigenvectors as well as matrix pseudoinverse. Several examples of implementation using Matlab are attached. The Vivado High-Level Synthesis tools and libraries were used for final implementation. After the brief introduction into the FPGA fundamentals the thesis continues with a description of implemented blocks. The results of each variant were compared in terms of timing and FPGA utilization. The selected block has been validated on the development board and its arithmetic precision was analyzed.
|
|
|
Acceleration of LZ4 Compression Algorithm in FPGA
Marton, Dominik ; Martínek, Tomáš (referee) ; Matoušek, Jiří (advisor)
This project describes the implementation of an LZ4 compression algorithm in a C/C++-like language, that can be used to generate VHDL programs for FPGA integrated circuits embedded in accelerated network interface controllers (NICs). Based on the algorithm specification, software versions of LZ4 compressor and decompressor are implemented, which are then transformed into a synthesizable language, that is then used to generate fully functional VHDL code for both components. Execution time and compression ratio of all implementations are then compared. The project also serves as a demonstration of usability and influence of high-level synthesis and high-level approach to design and implementation of hardware applications known from common programming languages.
|
|
|
High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
|
|
| |
|
|
Mapping of Algorithms to FPGA Using High-Level Synthesis Tools
Kupka, David ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis deals with ways to describe hardware. It presents the methods used in the synthesis of the description and then it compares on a set of algorithms currently common low level description in VHDL with the newly emerging high-level synthesis, where a component is described at a algorithmic level in higher programming language. The object of comparison is the ratio of time required for implementation and optimality of the resulting components.
|
guest ::
