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National Repository of Grey Literature

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	Platforma pro rychlý vývoj rekonfigurovatelného zpracování obrazu Kovář, Bohumil ; Kloub, Jan ; Schier, Jan ; Heřmánek, Antonín This paper outlines a proposed architecture for an integrated partial rapid prototyping dynamic reconfigurable system-on-a-chip, targeted at embedded real-time video and image processing. Detailed record
	Accelerator for Decoding Convolution and Reed-Solomon Code Kloub, Jan ; Heřmánek, Antonín Paper describes implementation of hardware accelerators for decoding convolution and Reed-Solomon code and using accelerators in Matlab. Detailed record
	Simulation of TEQ equalizers in ADSL toolbox: experiment results Mazanec, Tomáš ; Heřmánek, Antonín This report presents simulation results of ADSL time domain equalizers (TEQ) in our toolbox. Conclusions discuss "water-filling" bitload algorithm and compare it to others. Detailed record
	ADSL - equalization techniques Mazanec, Tomáš ; Heřmánek, Antonín The work presents the state of the art in digital signal processing in ADSL physical layer. Mainly, the equalization techniques are studed. The basic and advanced equalization algorithms are presented (both in time and frequency domain) and their characteristics are discussed. Detailed record
	Optimization of Finite Interval CMA Implementation for FPGA Šůcha, P. ; Heřmánek, Antonín ; Schier, Jan ; Hanzálek, Z. Detailed record
	Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping Líčko, Miroslav ; Schier, Jan ; Pohl, Zdeněk ; Kadlec, Jiří ; Tichý, Milan ; Matoušek, Rudolf ; Heřmánek, Antonín Detailed record
	Recursive Finite Interval Constant Modulus Algorithm for blind equalization Heřmánek, Antonín ; Regalia, P. In the paper, we reexamine the Finite Interval Constant Modulus Algorithm (FI-CMA) proposed by P.Regalia and we present our modifications leading to its recursive form. The proposed modifications are based on recursive updates of QR decomposition. The presented results shows the computation savings and ability to use Recursive FI-CMA for tracking time variant channels. Detailed record
	Floating-Point-Like Arithmetic for FPGA Matoušek, Rudolf ; Líčko, Miroslav ; Heřmánek, Antonín ; Softley, C. In recent years we have investigated the use of a logarithmic number representation as an alternative to floating-point. Efficient techniques have been developed to facilitate arithmetic comparable to single precision floating-point in the logarithmic domain. Detailed record
	Prototyping of DSP algorithms on FPGA Líčko, Miroslav ; Tichý, Milan ; Heřmánek, Antonín ; Matoušek, Rudolf ; Pohl, Zdeněk Poster describes an algorithm development process for FPGA. The process is shown on the example of an implementation of the QR RLS algorithm. Detailed record
	RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic Kadlec, Jiří ; Albu, F. ; Softley, Ch. ; Matoušek, Rudolf ; Heřmánek, Antonín Detailed record

National Repository of Grey Literature : 24 records found   1 - 10  jump to record:

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2	HEŘMÁNEK, Aleš

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