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> RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic
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Original title:
RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic
Authors:
Kadlec, Jiří
;
Albu, F.
;
Softley, Ch.
;
Matoušek, Rudolf
;
Heřmánek, Antonín
Document type:
Research reports
Year:
2001
Language:
eng
Series:
Research Report
, volume: 2036
Keywords:
digital signal processing
;
embedded compilation
;
logaritmic arithmetic
Project no.:
AV0Z1075907
(
CEP
),
HSLA 33544
,
LN00B096
(
CEP
)
Funding provider:
ESPRIT, GA MŠk
Institution:
Institute of Information Theory and Automation AS ČR (
web
)
Document availability information:
Fulltext is available at the institute of the Academy of Sciences.
Original record:
http://hdl.handle.net/11104/0130827
Permalink:
http://www.nusl.cz/ntk/nusl-34901
The record appears in these collections:
Research
>
Institutes ASCR
>
Institute of Information Theory and Automation
Reports
>
Research reports
Record created 2011-07-01, last modified 2024-01-26
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