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Transformation from C to VHDL Language
Mecera, Martin ; Kolář, Dušan (referee) ; Masařík, Karel (advisor)
The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.
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Process Inspector Tool Functionality Extension
Opršal, Martin ; Masařík, Karel (referee) ; Kreslíková, Jitka (advisor)
This master's thesis deals with process management, especially the general principles that lead to improvements in company processes. It's looking for methods to facilitate the identification and description processes. There are those applications that have just the identification and description of the process easier. Following is a description of the practical implementation of this application to Microsoft SharePoint.
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Transformation between the Microprocessor's Description Language and the Hardware Language
Novotný, Tomáš ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.
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Implementation of General Disassembler
Přikryl, Zdeněk ; Masařík, Karel (referee) ; Lukáš, Roman (advisor)
This thesis presents the process of creating disassembler for new designed processors. We demand automatic generation of the disassembler. Instruction set for processor is modeled by specialized language ISAC, which offers resources for description of the instruction set. For example it describes format of instruction in the assembly language or format of instruction in the binary form or behavior of this instruction. Internal model is coupled finite automata, which describes relation of textual form of the instruction and binary form of the instruction in formal way. The code of disassembler is generated from the internal model. This disassembler accepts program in binary code at the input and generate equivalent program in assembly language at the output.
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Syntax-Directed Editor
Šuška, Boris ; Masařík, Karel (referee) ; Kolář, Dušan (advisor)
This thesis is dealing with integration of available lexical analyzer generator tools and presents concept of parallel syntax analysis based on block-oriented syntax analysis. Results will be used during development of syntax-directed editor under Eclipse platform latter.
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Code Analysis and Transformation To a High-Level Language
Křoustek, Jakub ; Masařík, Karel (referee) ; Meduna, Alexandr (advisor)
This paper describes methods and procedures used for code analysis and transformation. It contains basic information of a science discipline called reverse engineering and its use in information technologies. The primary objective is a construction of a generic reverse compiler or decompiler, i.e. tool that can recompile from binary form (optionally from symbolic machine code) to a high level language. This operation is highly dependent on the concrete instruction set and processor architecture. This problem is solved with description of semantic of each instruction by a special language designed for this use. The output is the high level language code and is functionally equivalent to the input. The program is therefore able to work with each instruction set and code written by it can be transformed into the chosen high level language. This proposal is implemented in practice as a part of project Lissom. Generic decompiler is completely new idea. The thesis contains entirely new techniques from theory of compilers and optimizations made by the author.
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