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Software for digital filter verification
Tesařík, Jan ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
Diploma thesis deals with design of verification environment for analyzing systems with digital filters. Verification environment is written in SystemVerilog language and it is generated by program, which is also providing generation of input data for system of filters. Matlab environment is used for gaining the reference data. The simulation of the designed involvement with digital filters is performed by program ModelSim. The most watched parameter is functional coverage which indicates how big part of the HDL description has been tested.
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Formal verification of RISC-V processor with Questa PropCheck
Javor, Adrián ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.
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An Encoder and Decoder of an Error-correction Code for Programmable Read-only Memories
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with theory of coding, analyses current groups of error correction codes and describes features and parametres of chosen representatives of these groups. By comparing these parametres along with given criteria it choses extended Hamming code as suitable code for securing read-only-memories (ROM). For this code it choses way of realization of synthetisable modules of coder and decoder and describes their design. The work describes design of synthetizable modules of coder and decoder in VHDL. Then it explains functionality of created application which is able to generate these synthetisable modules. For verification of generated modules it creates authentication environment. Part of this environment is also model of ROM allowing writing of any error value into the memory. In the end it automatically verifies generated modules of coder and decoder with various width of input information vector.
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Proprietary communication protocol for data transfer between FPGA and PC
Beneš, David ; Pavlík, Michal (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with the design and implementation of a communication protocol which allows for data transfer between a PC and an FPGA. The designed protocol supports functions such as ´write´, ´read´ and ´write with a confirmation´ with a memory. Another supported function is autonomous transfer of telemetry data from an FPGA to a PC. Described in the theoretical part of the thesis, is the communication channel that is used for packet transfer. In the practical part are defined the packets and the protocol is implemented on PC in the form of a library and as a module on FPGA.
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FPGA Implementation of RMAP Initiator and Target
Walletzký, Ondřej ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
The thesis deals with design and implementation of controllers for the RMAP protocol, which is used by SpaceWire network endpoints to access memory contents of another endpoint. The theoretical research introduces concepts of the SpaceWire network, then describes the RMAP protocol and the AMBA AHB bus interface in detail. The practical part of this thesis then uses this information to design and implement controllers for the RMAP protocol. It first defines an architecture of these controllers, then describes design of individual blocks based on this architecture. As a next step, the thesis describes methods used to verify designed controllers and to test these controllers in an FPGA chip. Finally, an analysis of maximum frequency and usage of FPGA resources is done based on estimates provided by the synthesis tool.
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Air Traffic Simulation with HackRF One
Mikan, Lukáš ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
Práce se zabývá problematikou simulace letového provozu v kontextu multilateračního přehledového systému. Technika multilaterace počítá polohu letounu coby průsečík hyperboloidů na základě rozdílů v čase příchodu zpráv z palubního transpondéru na různé pozice přijímacích antén. Při nahrazení každé antény SDR modulem lze vzdušný provoz nasimulovat pomocí umělých ADS-B zpráv, které jsou ve správných časech přivedeny do jednotlivých anténních vstupů. V této práci je použito SDR HackRF One, jehož hardware i firmware byl modifikován pro dosažení úzce synchronizovaného vysílání z potenciálně libovolného počtu propojených HackRF jednotek. Zde popsané úpravy zajišťují shodný kmitočet i fázi vzorkovacího hodinového signálu na všech HackRF, stejně jako současné spuštění přenosu. Ve druhé části práce je představeno algoritmické řešení umožňující sestavit fiktivní vzdušný scénář s libovolným počtem letů i přijímacích antén. Výstupem je sada datových streamů vhodná pro vyslání skrz synchronizovaná HackRF. Každý stream odpovídá specifické poloze antény v krajině a obsahuje přesně načasované zprávy standardu ADS-B, zakódovány pulzně-poziční modulací a převedeny na IQ vzorky. Celý systém umožňuje testovat správnou funkci reálného multilateračního sledovače, jako je například produkt MSS od firmy ERA, a.s.
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Spectrum analyzer based on ASIC
Eliáš, Josef ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This term project is focused on a design of spectral analyzer based on fast Fourier transform. There is sigma-delta analog to digital converter realized on Department of Microelectronics as ASIC. FFT was implemented into Spartan S3 board kit. This kit is based on FPGA from Xilinx Company that provides various optimized components for his FPGA. Depending on this component was created FFT 10th order in 10 bit resolution. Results are displayed on VGA monitor.
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Radar receiver beamforming implementation in FPGA
Bárta, Jakub ; Dvořák, Vojtěch (referee) ; Bohrn, Marek (advisor)
This thesis deals with design and implementation of digital beamformer for 3D radar. The text of this thesis contains derivation of beamforming algorithm and detailed description of it’s implementation on development kit with Cyclone V circuit. At the end of the thesis the beamformer design is verified and it’s further usage is discused.
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Autonomous bathroom airconditioner system
Zapletal, Ladislav ; Dvořák, Vojtěch (referee) ; Pavlík, Michal (advisor)
The work deals with the design, theoretical analysis and implementation procedure of the system, which according to the collected data adequately switch heating mirrors pads, exhaust ventilation system, and according to the needs open and close the heating valve to work as a thermostat. The aim was to construct a system that is based on obtained data to separately switch peripherals according to set values and so respond to the current changes of climatic conditions in the measuring point. The work also explains the components of the device and their mutual involvement. It also lists examples of program code that were used to create algorithms in microcontroller and PC applications.
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Unified verification environment for digital part of automotive mixed-signal integrated circuits
Petráš, Samuel ; Dvořák, Vojtěch (referee) ; Prokop, Roman (advisor)
This thesis is concerned with unified verification environment for the verification of small designs of the digital part of integrated circuits with mixed signals. By unified verification environment is meant an environment suitable for both simulation and emulation. The first chapter describes the current verification methods of such designs. The second chapter presents the requirements that emulation places on the verification environment implemented according to the Universal Verification Methodology (UVM) and the attached implementation of proposed environment. The third chapter contains practical knowledge gained during the implementation of the unified verification environment, problems and their solutions, as well as several comparisons between simulation and emulation.
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