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Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.
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Protection of highspeed communication systems
Smékal, David ; Martinásek, Zdeněk (referee) ; Hajný, Jan (advisor)
The diploma thesis deals with 128–bit AES data encryption and its implementation in FPGA network card using VHDL programming language. The theoretical part explains AES encryption and decryption, its individual steps and operating modes. Further was described the VHDL programming language, development environment Vivado, FPGA network card Combo–80G and configurable framework NetCOPE. The practical part is the implementation of AES–128 in VHDL. A simulation was used to eliminate errors, then the synthesis was performed. These steps were made using Vivado software. Last step of practical part was testing of synthesized firmware on COMBO–80G card. Total of 4 projects were implemented in FPGA card. Two of them were AES encryption and decryption with ECB mode and another two describe the encryption and decryption with CBC mode.
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Advanced Electronic Circuits Simulation Methods
Kocina, Filip ; Kozek, Martin (referee) ; Kyncl, Jan (referee) ; Kunovský, Jiří (advisor)
Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.
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Design of multipurpose generator of low- and high-frequency sub-bands
Caban, Dominik ; Brančík, Lubomír (referee) ; Šotner, Roman (advisor)
The thesis focuses on the generation of harmonic and non-harmonic waveforms in the low and high-frequency domains. The thesis aims to design and implement a portable multipurpose signal generator with a user interface powered by its own battery. The design focuses on the implementation of a function generator, a high-frequency generator, and a pulse generator with Gaussian characteristics within a single portable device. The thesis describes an introduction to signal generators, the selection of the individual components, the design procedure for each circuit, and their subsequent hardware implementation either within the development kit or the final product.
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Advanced Electronic Circuits Simulation Methods
Kocina, Filip ; Kozek, Martin (referee) ; Kyncl, Jan (referee) ; Kunovský, Jiří (advisor)
Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.
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Fast multiplication in the field GF(2n)
Bajtoš, Marek ; Žemlička, Jan (advisor) ; Šaroch, Jan (referee)
Title: Fast multiplication in the field GF(2n ) Author: Marek Bajtoš Department: Department of Algebra Supervisor: doc. Mgr. et Mgr. Žemlička Jan, Ph.D., Department of Algebra Abstract: In this bachelor thesis we research how to optimize multiplication with a fixed element of finite field which can be useful for implementation of crypto- graphic algorithms in lightweight cryptography. We will represent effectivity of multiplication by number of XOR operation needed for implementation of matrix which represent some fixed element of finite field. We prove that some matrix re- presents multiplication with some element of finite field if and only if the minimal polynomial of matrix is irreducible. We also prove theorems describing conditi- ons which matrix must satisfy so matrix can be implemented with only 1 or 2 XOR operations. At the end of the thesis we show construction of circulant MDS matrices which uses elements of finite field with low XOR count so they can be easily implemented. Keywords: lightweight cryptography, finite field, XOR, MDS matrix
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Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.
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Protection of highspeed communication systems
Smékal, David ; Martinásek, Zdeněk (referee) ; Hajný, Jan (advisor)
The diploma thesis deals with 128–bit AES data encryption and its implementation in FPGA network card using VHDL programming language. The theoretical part explains AES encryption and decryption, its individual steps and operating modes. Further was described the VHDL programming language, development environment Vivado, FPGA network card Combo–80G and configurable framework NetCOPE. The practical part is the implementation of AES–128 in VHDL. A simulation was used to eliminate errors, then the synthesis was performed. These steps were made using Vivado software. Last step of practical part was testing of synthesized firmware on COMBO–80G card. Total of 4 projects were implemented in FPGA card. Two of them were AES encryption and decryption with ECB mode and another two describe the encryption and decryption with CBC mode.
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